AI-Driven Pre-Silicon Verification Engineer

Intel Corporation; Leixlip; Hybrid; EUR 53,000 - 99,000; Full time

Job summary

Intel Corporation in Ireland, Leixlip, invites an IP Design Verification Engineer to join a highly skilled design/verification team for NIC, IPU and AI hardware. You will craft verification plans, build test benches, and develop environments to validate complex IPs, using AI-augmented verification to enhance coverage and bug detection in pre-silicon stages.

The role requires 5+ years in functional verification with SystemVerilog, OVM/UVM, and formal methods.

Qualifications

• Bachelor's degree required in electrical/computer engineering or related.
• 5+ years in functional design verification of ASIC/SoC/FPGA with SystemVerilog, OVM/UVM, debugging tools.
• Proficiency in creating IP test environments and/or formal verification methods.

Responsibilities

• Develop and execute IP verification plans covering microarchitecture specs.
• Design and implement test benches and verification environments for functionality and reliability.
• Utilize AI and simulation models to analyze power and timing and uncover bugs.
• Debug, identify root causes, and implement corrective actions for failing tests pre-silicon.
• Collaborate with architects, designers, DFT, and emulation/bring-up teams to ensure system-level correctness.
• Maintain and improve existing verification methodologies and infrastructure.
• Document test plans and participate in technical reviews to drive improvements.

Skills

Digital design fundamentals

Microarchitecture principles

Collaboration across teams

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields

Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

SystemVerilog

OVM/UVM

Debugging tools

Formal verification methods

Job description

Intel Corporation in Ireland, Leixlip, invites an IP Design Verification Engineer to join a highly skilled design/verification team for NIC, IPU and AI hardware. You will craft verification plans, build test benches, and develop environments to validate complex IPs, using AI-augmented verification to enhance coverage and bug detection in pre-silicon stages.

The role requires 5+ years in functional verification with SystemVerilog, OVM/UVM, and formal methods.