Junior/ Senior Digital Design Engineer

Credo; Hong Kong; On-site; HKD 320,000 - 520,000; Full time

Job summary

Credo in Hong Kong is seeking an experienced ASIC design engineer to drive microarchitecture and RTL implementation using Verilog/SystemVerilog. You will define reusable design methodologies, integrate complex IPs from internal teams and vendors, and perform block- and chip-level RTL verification as well as gate-level testing.

You will also back-end timing-closure support, ECO handling, chip bring-up, validation, and collaborate with Firmware and Applications teams.

Qualifications

• BS/MS in Electrical/Computer Engineering.
• BS degree with 2+ years of relevant experience, or recent graduate with MS degree.
• Knowledge of Verilog/System Verilog, UVM.
• Fluent with Verilog and System Verilog.

Responsibilities

• Microarchitecture and design in Verilog/System Verilog.
• Define and own ASIC design methodologies.
• Integrate complex IPs developed by internal groups as well other vendors.
• Block and Chip level RTL verification and gate-level netlist testing.
• Support other ASIC design activities such as Lint, CDC checks, formal verification, synthesis, and DFT.
• Support back-end engineers with timing-closure and ECOs.
• Chip bring up, validation and debug.
• Support Firmware development and Applications teams.

Skills

Verilog/SystemVerilog

UVM

Python

Communication skills

Education

BS/MS in Electrical/Computer Engineering

Tools

Synopsys DC

Cadence Incisive (IES)

Verdi

Job description

• Microarchitecture and design in Verilog/System Verilog.
• Define and own ASIC design methodologies.
• Integrate complex IPs developed by internal groups as well other vendors.
• Block and Chip level RTL verification and gate-level netlist testing.
• Support other ASIC design activities such as Lint, CDC checks, formal verification,synthesis, and DFT.

Duties

• Microarchitecture and design in Verilog/System Verilog.
• Define and own ASIC design methodologies.
• Integrate complex IPs developed by internal groups as well other vendors.
• Block and Chip level RTL verification and gate-level netlist testing.
• Support other ASIC design activities such as Lint, CDC checks, formal verification,synthesis, and DFT.

• Support back-end engineers with timing-closure and ECOs.
• Chip bring up, validation and debug.
• Support Firmware development and Applications teams.

Requirements

• BS/MS in Electrical/Computer Engineering.
• BS degree with 2+ years of relevant experience, or recent graduate with MS degree.

• Knowledge of Verilog/System Verilog, UVM.
• Fluent with Verilog and System Verilog.
• Good oral and written communication skills.
• Knowledge/experience with Python is nice to have.
• Knowledge of ASIC EDA tools such as Synopsys DC, Cadence Incisive (IES), Verdi etc. is nice to have.