Junior ASIC Digital Design Engineer - Verilog & Debug

Credo Technology (Hong Kong) Limited; Hong Kong; On-site; HKD 420,000 - 660,000; Full time

Job summary

Credo Technology (Hong Kong) Limited in Hong Kong is seeking an ASIC design engineer to drive mikcroarchitecture and RTL development in Verilog/SystemVerilog. You will own design methodologies and collaborate with IP teams and back-end timing groups to ensure successful silicon.

The role requires strong communication skills and experience with EDA tools; knowledge of Python is a plus. This onsite position offers opportunities to contribute across the full ASIC flow from design to bring-up.

Qualifications

• BS/MS in Electrical/Computer Engineering.
• 2+ years of relevant experience, or MS with recent graduation.
• Knowledge of Verilog/SystemVerilog and UVM.
• Fluent with Verilog and SystemVerilog.
• Good oral and written communication.
• Knowledge of Python is a plus.
• Knowledge of ASIC EDA tools like Synopsys DC, Cadence Incisive (IES), Verdi is a plus.

Responsibilities

• Design and microarchitecture in Verilog/SystemVerilog.
• Define and own ASIC design methodologies.
• Integrate IPs from internal groups and vendors.
• Block and chip level RTL verification and gate-level netlist testing.
• Support lint, CDC checks, formal verification, synthesis, and DFT.
• Support back-end engineers with timing-closure and ECOs.
• Chip bring up, validation and debug.
• Support firmware development and Applications teams.

Skills

Verilog

SystemVerilog

UVM

Python

Education

Electrical/Computer Engineering degree

Tools

Synopsys DC

Cadence Incisive (IES)

Verdi

Job description

Credo Technology (Hong Kong) Limited in Hong Kong is seeking an ASIC design engineer to drive mikcroarchitecture and RTL development in Verilog/SystemVerilog. You will own design methodologies and collaborate with IP teams and back-end timing groups to ensure successful silicon.

The role requires strong communication skills and experience with EDA tools; knowledge of Python is a plus. This onsite position offers opportunities to contribute across the full ASIC flow from design to bring-up.