Summer internship – Digital design engineer

Fast Forward; Cambridge; Hybrid; GBP 30,000 - 35,000; Full time

Benefits offered by this job

Mentorship from engineers

Flexible hybrid working environment

Open-source project experience

Job summary

lowRISC is seeking a Summer Intern in Cambridge to join our hardware engineering team. You will gain hands-on experience in digital design and verification for open-source semiconductor projects, with exposure to SystemVerilog, UVM, and Python tooling.

Ideal candidates are pursuing Computer Science or Electronic Engineering, in 2nd year or above, with interest in hardware design and verification. The role offers a competitive internship salary and a flexible hybrid work arrangement.

Qualifications

• Pursuing Computer Science, Electronic Engineering or related field (2nd year Bachelors or part way through Masters/PhD).
• Experience or interest in digital design or verification.
• Familiarity with hardware description languages and scripting for verification is plus.

Responsibilities

• Assist digital design workflows using SystemVerilog or equivalent.
• Develop testbenches and automated verification scripts (UVM or equivalent).
• Analyze verification results to improve hardware reliability and contribute to open-source repos.

Skills

Digital design

Design verification

Python scripting

Education

2nd year Bachelor's or higher

Tools

SystemVerilog

UVM

Python

Job description

Location: Cambridge, UK

Duration: 10 to 12 weeks (Mid-June to September 2027)

Paid internship: £30k (undergrad) up to £35k (postgrad)

Please apply by 30th January 2027

About lowRISC

Imagine the innovations we could achieve together if production-ready commercial-grade IP components and engineering systems were available to everyone, for free.At lowRISC, we believe that open-source development can transform the semiconductor industry.

Our Ibex CPU and OpenTitan Root of Trust projects have been taken to production silicon, partnering with world-leading organisations including Google, combining open-source approaches with best practice chip design methodologies.

lowRISC is a non-profit Community Interest Company: with a business model that includes member fees and engineering services we have shown that it is possible to run world-leading projects collaboratively for everyone’s benefit. Originally a spinoutfrom Cambridge University’s Computer Lab, our UK team is based in Cambridge and our Switzerland team is based in Zurich.

The role

We are looking for a Summer Intern with an interest in hardware design to support our engineering teams. This internship offers hands‑on exposure to digital design and design verification through open-source projects of commercial grade quality.

You may work on:

• Digital design workflows using SystemVerilog or equivalent
• Developing testbenches and automated verification scripts using UVM or equivalent
• Analysing verification results to improve hardware reliability
• Contributing to open-source repositories and documentation

About you

We are looking for students who:

• Are studying Computer Science, Electronic Engineering or related fields 2nd+ year Bachelor's or part way through a Master's or PhD
• Have experience or interest in digital design or design verification
• Are comfortable with a hardware description language and Python or scripting for verification
• Are curious, proactive, and enjoy collaborative problem solving

Bonus skills (not required):

• Familiarity with RISC-V architectures
• Knowledge of UVM / SystemVerilog testbenches

What we offer

• Competitive salary £30k for undergrad, and up to £35k for a postgrad
• Mentorship from engineers leading open-source hardware projects
• Flexible hybrid working environment
• Opportunity to contribute to globally used open-source projects
• Collaborative project based culture

We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.

If you need any adjustments made to the application or selection process, please let us know by emailing [e-mail]