Staff Digital IC Design Engineer — SystemVerilog, DFT, Lead

Power Integrations; Cambridge; On-site; GBP 60,000 - 80,000; Full time

Benefits offered by this job

Private healthcare

Enhanced Sick Pay

Pension scheme

Employee Assistance Programme

Job summary

Power Integrations is hiring a Staff Digital IC Design Engineer in Cambridge. In this role, you will develop functional digital blocks for mixed signal ASICs while collaborating with various teams. Key responsibilities include RTL design in SystemVerilog and verification procedures.

The ideal candidate has an MSc/MEng or PhD in Electronics Engineering, 5 years of experience in digital IC design, and knowledge of best practices in digital design methods.

Qualifications

• Minimum 5 years’ experience in digital IC design using standard cell libraries.
• In depth knowledge of best-practice digital design methods.
• Expertise in executing designs via synthesised digital design flow.

Responsibilities

• Develop functional digital blocks for complete mixed signal ASICs.
• Support product definition and architecture for FPGA emulation.
• Complete RTL design in SystemVerilog for system requirements.
• Create block-level test benches for verification.
• Lead digital design methodology improvements within the company.

Skills

Digital IC design

SystemVerilog

Logical synthesis

Mixed-signal oscilloscopes

TCL/Python scripting

Education

MSc/MEng or PhD in Electronics Engineering

Job description

Power Integrations is hiring a Staff Digital IC Design Engineer in Cambridge. In this role, you will develop functional digital blocks for mixed signal ASICs while collaborating with various teams. Key responsibilities include RTL design in SystemVerilog and verification procedures.

The ideal candidate has an MSc/MEng or PhD in Electronics Engineering, 5 years of experience in digital IC design, and knowledge of best practices in digital design methods.