Digital Design Engineer - UK Visa Sponsorship Available

EasyInfoBlog.com LLC; Southampton; Hybrid; GBP 81,000 - 99,000; Full time

Benefits offered by this job

Benefits

Job summary

A semiconductor company based in Southampton is seeking a Digital IC Design Lead to join their growing team. This senior technical leadership role combines hands-on digital IC design expertise and project leadership. The ideal candidate should have a BEng or MEng in a relevant field and at least 5 years of experience in digital design, with proficiency in Verilog, SystemVerilog, and/or VHDL. The role offers a hybrid work model and Visa sponsorship is available.

Qualifications

• 5+ years experience in digital or mixed signal design.
• 1+ years experience in a people management or technical leadership role.
• Hands‑on experience in digital IC design using Verilog, SystemVerilog, and/or VHDL.

Skills

Digital IC design expertise

People management

Technical leadership

Verilog

SystemVerilog

VHDL

Education

BEng or MEng in Engineering, Electronics, or a related discipline

Tools

JIRA

Confluence

Job description

Digital IC Design Lead – Southampton (Hybrid) – £90k + Benefits

My client is a high growth semiconductor business with a strong focus on innovation across display, video, AI data processing, and wireless connectivity. They operate in a modern, engineering‑led environment and are continuing to expand their IC Development capability.

They are now seeking an experienced IC Digital Lead to join their growing team. This is a senior technical leadership role, combining hands‑on digital IC expertise with people and project leadership.

Location: Southampton, Hampshire (Hybrid)

Visa Sponsorship: Available

Essential requirements:

• BEng or MEng in Engineering, Electronics, or a related discipline
• 5+ years experience in digital or mixed signal design
• 1+ years experience in a people management or technical leadership role
• Hands‑on experience in digital IC design using Verilog, SystemVerilog, and/or VHDL

Desirable experience:

• Mixed signal design exposure
• Familiarity with the full ASIC front‑end and back‑end flow
• Python scripting
• Experience using tools such as JIRA and Confluence

Apply below!