Staff Design Verification Engineer – AI-Driven Networking

AMD; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Job summary

AMD is seeking a Staff Design Verification Engineer in Cambridge to verify next-generation networking silicon and SmartNIC technologies. You will shape verification strategies, develop robust plans, and drive automation across simulation, emulation, and data-driven analytics.

You will collaborate with architecture, hardware, and firmware teams across sites, building directed tests, debugging complex issues, and advancing AI-enabled productivity in verification workflows.

Qualifications

• Experience in IP-level ASIC verification.
• Proficient with UVM testbenches and SystemVerilog.
• Strong debugging of RTL/firmware with industry tools.
• Proficiency in Verilog, SystemVerilog, C, and C++.
• Experience building UVM-based verification frameworks.
• Scripting in Python/Perl/Shell.
• Familiarity with data analytics and AI-enabled workflows.
• Experience applying AI/ML tools to verification or productivity.
• Knowledge of SystemC and TLM is a plus.
• Exposure to networking, Ethernet, or SmartNIC architectures is desirable.

Responsibilities

• Collaborate with architects and hardware/firmware engineers to define verification requirements.
• Create comprehensive verification plans covering hardware, firmware, software, and system-level use cases.
• Develop directed and constrained-random tests and verification environments.
• Estimate verification effort and identify needed enhancements to environments.
• Debug test failures and coordinate with RTL/firmware teams to fix defects.
• Drive functional and code coverage closure through test development and analysis.
• Contribute to verification methodologies across simulation, emulation, and data analytics.
• Develop automation solutions and AI-driven workflows to boost efficiency and coverage.

Skills

ASIC verification

UVM testbenches

SystemVerilog

Verilog

Python

AI-assisted engineering

Debugging RTL

Data analytics

Automation scripting

Communication across sites

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

UVM

SystemVerilog

Verilog

Python

Job description

AMD is seeking a Staff Design Verification Engineer in Cambridge to verify next-generation networking silicon and SmartNIC technologies. You will shape verification strategies, develop robust plans, and drive automation across simulation, emulation, and data-driven analytics.

You will collaborate with architecture, hardware, and firmware teams across sites, building directed tests, debugging complex issues, and advancing AI-enabled productivity in verification workflows.