SOC Performance Modeling Architect – Platform Excellence

Apple Inc.; Cambridge; On-site; GBP 147,000 - 221,000; Full time

Benefits offered by this job

Employee stock programs

Relocation assistance

Tuition reimbursement

Comprehensive benefits

Job summary

Apple Inc. in Cambridge, UK, seeks an upbeat SOC Performance Modeling SW Architect to shape the architecture of future devices.

You will work on performance models and infrastructure within the Hardware Technologies organization, collaborating across SOC architecture, design, power, and software teams. You will translate design space studies into high-performance C++ models, participate from early exploration to post-silicon correlation, and ensure the simulator is maintainable and AI-friendly

Qualifications

• Experience in hardware architecture and design issues.
• Experience coding in C++ and Python and binding C++ to other languages.
• Experience with data structures and algorithms.
• Experience using software models to collect behavioral characteristics and transform that data into performance analysis.

Responsibilities

• Appreciate the good parts of C++, and leverage the language to maximize model utility.
• Develop APIs that can be used by non-expert C++ developers.
• Train AI agents and non-expert developers on idiomatic code and methods.
• Help ensure our codebase is structured for AI-assisted development tools.
• Write clear, self-documenting code with consistent conventions and well-organized modules.
• Learn about state of the art SoC IP and chip-level architecture.
• Work on data analysis pipelines, visualization methodologies, and regression testing.
• Present simulation results clearly.

Skills

C++

Python

Data analysis

Algorithms

Education

MS or PhD in CS, EE or related field

Tools

Compiler Explorer

Job description

Apple Inc. in Cambridge, UK, seeks an upbeat SOC Performance Modeling SW Architect to shape the architecture of future devices.

You will work on performance models and infrastructure within the Hardware Technologies organization, collaborating across SOC architecture, design, power, and software teams. You will translate design space studies into high-performance C++ models, participate from early exploration to post-silicon correlation, and ensure the simulator is maintainable and AI-friendly