Silicon Logic Design Engineer: RTL & IP Integration

Graphcore; Bristol; On-site; GBP 70,000 - 100,000; Full time

Benefits offered by this job

Flexible working

Generous annual leave

Private medical insurance

Health cash plan

Dental plan

Pension (matched up to 5%)

Life assurance

Income protection

Parental leave policy

Employee assistance programme

Snacks and barista bar

Job summary

Graphcore Bristol seeks a Silicon Logical Design Engineer to deliver high quality micro-architecture specifications and RTL for Graphcore chips. The role involves integrating IP into top-level SoCs, building robust environments, and performing SoC-level synthesis, linting, CDC/RDC and timing checks.

You will support verification and physical design teams, debug cross-hierarchy issues and push automation. Strong SystemVerilog/VHDL and Python/Tcl skills are required, with a collaborative,

Qualifications

• Degree in Computer Science, Engineering or a related subject.
• Digital design experience in a relevant industry.
• Be highly motivated, a self-starter, and a team player.
• Ability to work across teams and find solutions to problems.
• Ability to solve design issues through programming (Python, Tcl).
• Strong competency in SystemVerilog or VHDL.
• Knowledge of digital design flows.
• Capable of managing time and priorities.

Responsibilities

• Integrate IP and subsystems into top-level SoC designs.
• Develop and maintain build and configuration environments.
• Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level.
• Support verification and physical design teams through clean interface hand-offs.
• Debug and resolve integration-related issues across multiple hierarchies.
• Contribute to the continuous improvement of integration flows and automation.
• Producing high quality microarchitecture and other documentation.
• Ensure good communication between sites to maintain consistent working practices.

Skills

IP integration

Synthesis

Linting

CDC/RDC

Timing checks

Debugging

Documentation

Communication

Python

Tcl

SystemVerilog

VHDL

Digital design flows

Time management

Education

Degree in Computer Science, Engineering or a related subject

Tools

Python

Tcl

SystemVerilog

VHDL

Job description

Graphcore Bristol seeks a Silicon Logical Design Engineer to deliver high quality micro-architecture specifications and RTL for Graphcore chips. The role involves integrating IP into top-level SoCs, building robust environments, and performing SoC-level synthesis, linting, CDC/RDC and timing checks.

You will support verification and physical design teams, debug cross-hierarchy issues and push automation. Strong SystemVerilog/VHDL and Python/Tcl skills are required, with a collaborative,