Senior Test Engineering Lead, AI Accelerator Chips

Fractile Ltd.; Greater London; Hybrid; GBP 120,000 - 180,000; Full time

Benefits offered by this job

Equity

Private Medical

Dental & Vision

Contributory Pension

25 Days Holiday

Job summary

Fractile Ltd. in the United Kingdom is seeking a senior Semiconductor Test Engineering leader to drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices.

You will oversee all aspects of production test development, from DFT strategy to high-volume manufacturing ramp, leading internal teams and coordinating with external partners to deliver robust, cost-effective test solutions for cutting-edge AI accelerators.

Qualifications

• 8+ years in semiconductor test engineering, including leadership or technical lead roles.
• Deep experience with ATE test development (e.g., Advantest 93K, Teradyne).
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high-speed interface testing.
• Experience managing external test development partners or OSATs.
• Proven ability to lead and mentor test engineering teams.
• Solid background in advanced CMOS nodes and familiarity with advanced packaging test challenges.
• Expertise in silicon debug, characterization, and correlation across ATE and system-level environments.
• Ability to collaborate across design, architecture, product engineering, packaging, and operations.

Responsibilities

• Drive the manufacturing test strategy for an AI accelerator chip featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and advanced packaging (e.g., 2.5D/3D, chiplet).
• Lead and manage a team of chip test engineers responsible for test planning, test program development, pattern bring-up, silicon characterization, debug, and optimization.
• Manage subcontracted test development partners (OSATs, ATE vendors, external engineering services). Includes scoping, technical oversight, schedule tracking, and quality control of deliverables.
• Define and drive test software architecture, DFT usage, and test pattern development strategies for high-speed logic, SRAM, DRAM, and High Speed IO blocks.
• Work closely with design, DFT, product engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success.
• Oversee test development for high speed interfaces such as PCIe Gen6 and multi-GHz LPDDR.
• Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system-level tests).
• Lead silicon bring-up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities.
• Define KPIs and metrics for subcontractor performance, test coverage, yield, time-to-test, and cost optimization.
• Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure.
• Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die-to-die IO testing).
• Support qualification, reliability testing, and high-volume manufacturing transfer.

Skills

ATE test development

DFT (scan, ATPG, LBIST, MBIST)

Leadership

CMOS nodes

Testing memory interfaces

Vendor management

Silicon debug

Test strategy

PCIe Gen6 testing

Tools

Advantest 93K

Teradyne

Job description

Fractile Ltd. in the United Kingdom is seeking a senior Semiconductor Test Engineering leader to drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices.

You will oversee all aspects of production test development, from DFT strategy to high-volume manufacturing ramp, leading internal teams and coordinating with external partners to deliver robust, cost-effective test solutions for cutting-edge AI accelerators.