Semiconductor Test Engineering Team Leader

Fractile; London Borough of Southwark; On-site; GBP 90,000 - 150,000; Full time

Benefits offered by this job

None

Job summary

Fractile is seeking a senior Semiconductor Test Engineering leader to drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices.

You will oversee test development, pattern bring-up, silicon characterization, and yield optimization, coordinating with design, packaging, and validation teams to ensure scalable, cost-effective test solutions.

Qualifications

• 8+ years in semiconductor test engineering or leadership roles.
• Deep experience with ATE test development (Advantest 93K, Teradyne).
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high-speed interface testing.
• Experience managing external test development partners or OSATs.
• Proven ability to lead and mentor test engineering teams.
• Solid background in advanced CMOS nodes and familiarity with external packaging test challenges.
• Expertise in silicon debug, characterization, and correlation across ATE and system-level environments.

Responsibilities

• Drive the manufacturing test strategy for AI accelerator chips with high-speed interfaces.
• Lead a team of test engineers for test planning, program development, pattern bring-up, and yield optimization.
• Manage subcontracted test development partners (OSATs, ATE vendors) with scope, oversight and quality control.
• Define test software architecture, DFT usage, and test pattern development strategies for high-speed logic and memory.
• Collaborate across design, packaging, validation, and operations to ensure robust test coverage and manufacturability.
• Oversee silicon bring-up, correlation, failure analysis, and yield improvement activities.
• Define KPIs for subcontractor performance, test coverage, and cost optimization.

Skills

ATE test development

DFT (scan ATPG LBIST MBIST)

memory testing

high-speed interface testing

external test development partners

team leadership

silicon debug & characterization

advanced CMOS nodes

advanced packaging test

Tools

Advantest 93K

Teradyne

Job description

About Fractile Fractile was founded in 2022 on the bet that, eventually, the world's most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts. The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

The Role We are seeking a senior Semiconductor Test Engineering leader to drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices. This role combines deep technical expertise in high-performance compute silicon with leadership responsibility for internal product engineering teams and external development partners. The successful candidate will oversee all aspects of production test development - from DFT strategy and ATE bring-up through silicon characterisation, yield optimisation, advanced packaging test, and high-volume manufacturing ramp - ensuring robust, scalable, and cost-effective test solutions for advanced AI accelerator platforms.

Key Responsibilities

Drive the manufacturing test strategy for an AI accelerator chip featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and advanced packaging (e.g., 2.5D/3D, chiplet). Lead and manage a team of chip test engineers responsible for test planning, test program development, pattern bring-up, silicon characterization, debug, and optimization. Manage subcontracted test development partners (OSATs, ATE vendors, external engineering services). Includes scoping, technical oversight, schedule tracking, and quality control of deliverables. Define and drive test software architecture, DFT usage, and test pattern development strategies for high-speed logic, SRAM, DRAM, and High Speed IO blocks. Work closely with design, DFT, product engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success. Oversee test development for high speed interfaces such as PCIe Gen6 and multi-GHz LPDDR. Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system-level tests). Lead silicon bring-up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities. Define KPIs and metrics for subcontractor performance, test coverage, yield, time-to-test, and cost optimization. Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure. Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die-to-die IO testing). Support qualification, reliability testing, and high-volume manufacturing transfer.

Required Qualifications

8+ years in semiconductor test engineering, including leadership or technical lead roles. Deep experience with ATE test development (e.g., Advantest 93K, Teradyne). Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high-speed interface testing. Experience managing external test development partners or OSATs. Proven ability to lead and mentor test engineering teams. Solid background in advanced CMOS nodes and familiarity with advanced packaging test challenges. Expertise in silicon debug, characterization, and correlation across ATE and system-level environments. Ability to collaborate across design, architecture, product engineering, packaging, and operations.

Preferred Qualifications

Experience with "AI/ML accelerator chips" or other high-performance compute ICs. Prior involvement with PCIe Gen5/Gen6 or LPDDR4/5/6 test methodologies. Familiarity with signal-integrity-aware test development and high-speed IO margining. Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

How we work

Ownership and execution: you will have full agency to drive your work forward Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generation