Senior Signal & Power Integrity Engineer — High‑Speed PCB

Lumai; Oxford; On-site; GBP 70,000 - 110,000; Full time

Job summary

Lumai, an Oxford-based optical compute innovator, seeks an experienced signal and power integrity engineer to own SI/PI across boards and packages. You’ll lead pre-layout channel studies, post-layout analyses, and optimisations to ensure reliable high-speed operation from chip to optical engine.

You will correlate simulations with hardware, sign off critical channels, and help build reusable design guidelines for future projects.

Qualifications

• Degree in electronic engineering, physics or related field.
• Proficiency with EM/circuit simulation suites (HFSS, SIwave, ADS, Sigrity/Clarity).
• Strong transmission line, S-parameters, crosstalk, eye/COM metrics knowledge.
• Experience with IBIS/IBIS-AMI for SerDes/memory simulations.
• Solid PDN design knowledge: impedance targets, decoupling, DC IR drop.

Responsibilities

• Run pre-layout channel studies to set routing topologies and stackups.
• Perform post-layout SI analysis: insertion/return loss, crosstalk, eye/COM with IBIS-AMI models.
• Design and optimise vias, breakouts, connector launches, transitions to optical engines.
• Set PDN impedance targets, decoupling strategies, and DC/AC PDN analysis.
• Support package/interposer/board co-simulation with ASIC teams.
• Correlate simulations with lab measurements using TDRs, VNAs, oscilloscopes.
• Evaluate PCB materials, connectors and cables with suppliers/fabricators.
• Build SI/PI methodology, libraries and design guidelines for reuse.

Skills

SI/PI experience

EM/Circuit sims

IBIS-AMI modeling

PDN design

Measurement skills

Scripting (Python)

Channel/topology knowledge

High-speed PCB/packaging

Education

Electronic engineering/Physics degree

Tools

HFSS/SIwave

ADS

Sigrity/Clarity

Job description

Lumai, an Oxford-based optical compute innovator, seeks an experienced signal and power integrity engineer to own SI/PI across boards and packages. You’ll lead pre-layout channel studies, post-layout analyses, and optimisations to ensure reliable high-speed operation from chip to optical engine.

You will correlate simulations with hardware, sign off critical channels, and help build reusable design guidelines for future projects.