Senior SerDes Validation Engineer – Satellite ASICs

MRL Consulting Group | Global Niche Technology Recruitment; Farnborough; On-site; GBP 90,000 - 120,000; Full time

Job summary

MRL Consulting Group | Global Niche Technology Recruitment is seeking a Senior SerDes Validation Engineer to join a team developing next-generation satellite communication solutions. You will work on advanced ASICs, high-speed interfaces and cutting-edge silicon products.

Responsibilities include validating SerDes PHYs, performing PVT validation, using oscilloscope, BERT, DCA and PNAX for eye diagrams and jitter, developing test plans, and creating automated tests in Python.

Qualifications

• Bachelor's or Master's degree in Electronic Engineering, Computer Engineering or related discipline.
• 8–13 years post-graduate experience in chip or system validation.
• Experience testing telecommunications or satellite systems (analog, RF, high-speed blocks).
• Strong knowledge of SerDes technology and RF fundamentals.
• Programming in Python, C/C++ for test automation.
• Familiarity with RF test equipment and debugging, plus JIRA/Confluence.

Responsibilities

• Validate high-speed SerDes PHYs and perform link bring-up, equalisation and testing.
• Execute chip and system validation across PVT conditions.
• Use oscilloscope, BERT, DCA and PNAX for eye diagrams and jitter testing.
• Develop and execute chip and system test plans with engineering teams.
• Create automated test solutions using Python and investigate root causes.
• Analyse data, support CI and contribute to product quality.

Skills

Python

C/C++

Test automation

SerDes

RF fundamentals

Education

Bachelor's degree in Electronic/Computer Engineering

Master's degree in Electronic/Computer Engineering

Tools

Oscilloscopes

BERT

DCA

PNAX

JIRA

Confluence

Job description

MRL Consulting Group | Global Niche Technology Recruitment is seeking a Senior SerDes Validation Engineer to join a team developing next-generation satellite communication solutions. You will work on advanced ASICs, high-speed interfaces and cutting-edge silicon products.

Responsibilities include validating SerDes PHYs, performing PVT validation, using oscilloscope, BERT, DCA and PNAX for eye diagrams and jitter, developing test plans, and creating automated tests in Python.