Senior/Principal FPGA Engineer: Design & Verification

FINTEC recruit Ltd; City of Edinburgh; On-site; GBP 65,000 - 95,000; Full time

Job summary

FINTEC recruit Ltd is seeking a Senior / Principal FPGA Engineer in Edinburgh to design, verify, and deliver robust FPGA solutions across complex programmes. You will own technical activities, capture requirements, and work with Systems, Hardware and Software teams to ensure smooth integration.

The role emphasizes strong VHDL/Verilog design, independent verification, and experience with Mentor Graphics tools and major FPGA flows.

Qualifications

• Strong FPGA design experience using VHDL and Verilog.
• Experience with Mentor Graphics tools (HDL Designer, ModelSim/Questa, Precision).
• Knowledge of Xilinx, Intel/Altera or Microsemi Actel flows (ISE, Vivado, Quartus).
• Experience specifying timing/area constraints for FPGA place and route.
• Independent FPGA verification experience using VHDL.
• Requirements capture and requirements management experience.
• FPGA version control and revision control knowledge.
• Ability to derive FPGA requirements from system/hardware needs.
• Confident debugging and cross-disciplinary collaboration.

Responsibilities

• Designing and developing FPGA solutions using VHDL-based techniques.
• Supporting verification using VHDL, Verilog, SystemVerilog.
• Collaborating with Systems, Hardware and Software teams for integration.
• Capturing requirements and translating them into FPGA requirements.
• Debugging FPGA designs and supporting hardware/system verification.
• Maintaining technical documentation and configuration management.
• Providing progress updates and coordinating engineering activities.

Job description

FINTEC recruit Ltd is seeking a Senior / Principal FPGA Engineer in Edinburgh to design, verify, and deliver robust FPGA solutions across complex programmes. You will own technical activities, capture requirements, and work with Systems, Hardware and Software teams to ensure smooth integration.

The role emphasizes strong VHDL/Verilog design, independent verification, and experience with Mentor Graphics tools and major FPGA flows.