Senior FPGA/ASIC Design Engineer — RTL & System Validation

Advanced Micro Devices, Inc.; City of Edinburgh; Remote; GBP 85,000 - 115,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD in Edinburgh seeks a senior FPGA/ASIC engineer to design, integrate, and validate high‑performance RTL for advanced IPs and subsystems across FPGA and ASIC platforms.

You will lead technical discussions, mentor junior engineers, and help shape best practices, collaborating with global teams on challenging hardware and software integration.

This role offers hands‑on ownership, visibility, and clear opportunities for career growth within a world‑class innovation environment.

Qualifications

• Strong experience with modern, complex digital processing architectures.
• Deep understanding of FPGA and ASIC design flows, tools, and system‑level design.
• Solid software development and integration skills.

Responsibilities

• Lead technical discussions and collaborate with system architects, hardware, and software engineers to define and deliver new features
• Act as a technical mentor to junior engineers through design reviews, best‑practice guidance, and day‑to‑day support
• Design and implement high‑quality, high‑performance RTL for new features, modules, and systems
• Develop software and scripts to configure, control, and test hardware modules and systems
• Create clear, detailed documentation describing designs and interactions with hardware and software components
• Debug complex system‑level issues, identify root causes, and partner with verification teams to deliver robust solutions
• Estimate development schedules and test‑environment needs, and support junior engineers with project planning
• Champion continuous improvement in design, validation, and development workflows

Skills

Digital processing architectures

FPGA design flows

ASIC design flows

System-level design

Software development

Job description

AMD in Edinburgh seeks a senior FPGA/ASIC engineer to design, integrate, and validate high‑performance RTL for advanced IPs and subsystems across FPGA and ASIC platforms.

You will lead technical discussions, mentor junior engineers, and help shape best practices, collaborating with global teams on challenging hardware and software integration.

This role offers hands‑on ownership, visibility, and clear opportunities for career growth within a world‑class innovation environment.