Senior FPGA Engineer

Avanti Recruitment Limited; Ely; On-site; GBP 70,000 - 100,000; Full time

Job summary

Avanti Recruitment Limited is seeking a Senior FPGA Engineer to join a specialist engineering and R&D business in the UK. You will own FPGA architecture across high-speed data acquisition, SoC-FPGA integration, DSP, and future CNN acceleration.

You will work with Xilinx Zynq UltraScale or similar platforms, taking ownership of RTL development, AXI/DMA data paths, and embedded Linux integration to drive real-time processing and edge AI capabilities.

Qualifications

• Hands-on RTL development experience in FPGA environments.
• Experience with SoC-FPGA platforms and integration.
• Strong knowledge of AXI, DMA and high-speed data paths.

Responsibilities

• Develop VHDL/Verilog/SystemVerilog for high-speed data paths.
• Handle ADC/LVDS data acquisition and data movement.
• Implement AXI interfaces and PS/PL integration.
• Manage DDR memory interfaces and streaming pipelines.
• Oversee clocking, timing closure and CDC.
• Develop FPGA DSP blocks and CNN acceleration as needed.
• Facilitate hardware bring-up and debugging.
• Integrate Embedded Linux (PetaLinux) on FPGA platforms.

Skills

RTL design

SoC-FPGA

AXI/DMA

Timing closure

FPGA DSP

Embedded Linux

Job description

We are recruiting for a Senior FPGA Engineer to join a specialist engineering and R&D business developing advanced sensing and Edge-AI technology.

This is a hands-on role with genuine ownership of the FPGA architecture, working across high-speed data acquisition, SoC-FPGA integration, real-time DSP and future CNN acceleration.

The Role

You will work with modern SoC-FPGA platforms, including technology such as Xilinx Zynq UltraScale, taking ownership of areas including:

• VHDL / Verilog / SystemVerilog development
• ADC and LVDS data acquisition
• DMA and high-speed data movement
• AXI interfaces and PS/PL integration
• DDR memory and streaming pipelines
• Clocking, timing closure and CDC
• FPGA DSP including filters, FFT and cross-correlation
• Hardware bring-up and debugging
• Embedded Linux / PetaLinux integration
• Longer-term FPGA-based CNN acceleration

The role will evolve from building a reliable high-speed acquisition platform into implementing real-time DSP and reconstruction directly within FPGA fabric.

What We're Looking For

You will be an experienced FPGA Engineer with strong hands-on RTL skills and experience with:

• SoC-FPGA platforms
• High-speed data acquisition
• AXI and DMA
• Timing closure and clock-domain crossing
• FPGA-based DSP
• Embedded software integration

Experience with Zynq UltraScale+, PetaLinux, PYNQ, Python/Jupyter, imaging, instrumentation or AI acceleration would be advantageous