Principal FPGA Design Engineer - Oxfordshire

Morgan McKinley; Oxford; On-site; GBP 80,000 - 120,000; Full time

Benefits offered by this job

Bonus

Generous benefits

Job summary

Morgan McKinley is seeking a Principal FPGA Design Engineer in the Oxfordshire area to lead the architecture and delivery of high-throughput FPGA subsystems. You will drive the full lifecycle from requirements to RTL implementation, lab validation, and product release.

The role requires hands-on experience with SystemVerilog/Verilog, AMD/Xilinx toolchains, and high-speed interfaces like PCIe/DMA. You will mentor mid/senior hardware engineers and champion CI/CD automation.

Qualifications

• Full-lifecycle FPGA design experience
• Strong SystemVerilog/Verilog with AMD/Xilinx toolchains
• Degree in Electronic Engineering or equivalent

Responsibilities

• Lead FPGA subsystem architecture for complex data platforms.
• Design/verify digital RTL (SystemVerilog/Verilog) with AMD/Xilinx toolchains.
• Optimize throughput, power, resources, and timing closure.
• Collaborate with ASIC, FW, and SW teams for board bring-up.
• Mentor hardware engineers and drive CI/CD automation.

Skills

FPGA design

SystemVerilog

Verilog

Vivado

PCIe

DMA

Python

Tcl

Make

Leadership

Education

Bachelor's degree in Electronic Engineering

Tools

AMD Xilinx tools

Vivado

Questa

Job description

Role: Principal FPGA Design Engineer

Location: Oxfordshire

Package: £80k - £120k + Bonus + Generous Benefits

About the Business:

We are partnering with a pioneering UK technology innovator developing next-generation medical device technologies. Operating globally, they combine hardware, custom silicon, and complex data processing to transform global healthcare and scientific research.

Role Overview:

A hands-on technical leadership and mentorship position, owning the architecture and delivery of high-throughput FPGA subsystems. You will drive designs across the full lifecycle-from initial requirements through RTL implementation, custom-ASIC bring-up, lab validation, and product release.

Key Responsibilities:

• System Architecture: Lead FPGA subsystem architecture for complex data platforms.
• RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains.
• Optimization: Maximize throughput, power efficiency, resource usage, and timing closure.
• Integration: Collaborate with ASIC, FW, and SW teams to support board bring-up.
• Leadership: Champion CI/CD automation and mentor mid/senior hardware engineers.

What We Need:

• Proven full-lifecycle FPGA design experience (architecture to hardware bring-up).
• Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa).
• Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging tools.
• Scripting for workflow automation (Python, Tcl, Make).
• Degree in Electronic Engineering or equivalent industry background.