Principal FPGA Design Engineer - Oxfordshire

Morgan McKinley (South West); Oxford; On-site; GBP 80,000 - 120,000; Full time

Benefits offered by this job

Bonus

Generous benefits

Job summary

Morgan McKinley (South West) is seeking a Principal FPGA Design Engineer in Oxfordshire to own the architecture and delivery of high-throughput FPGA subsystems from requirements through RTL and lab validation.

You will lead system architecture, RTL/verification using SystemVerilog, collaborate with ASIC, FW, and SW teams, and mentor mid/senior hardware engineers while driving CI/CD automation and design optimization.

Qualifications

• Full-lifecycle FPGA design experience (architecture to hardware bring-up).
• Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa).
• Hands-on experience with high-speed interfaces (PCIe) and lab debugging tools.
• Scripting for workflow automation (Python, Tcl, Make).
• Degree in Electronic Engineering or equivalent industry background.

Responsibilities

• System Architecture: Lead FPGA subsystem architecture for complex data platforms.
• RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains.
• Optimization: Maximize throughput, power efficiency, resource usage, and timing closure.
• Integration: Collaborate with ASIC, FW, and SW teams to support board bring-up.
• Leadership: Mentor mid/senior hardware engineers and champion CI/CD automation.

Skills

FPGA design

SystemVerilog/Verilog

PCIe

DMA

Python

Tcl

Make

Mentorship

Education

Electronic Engineering degree

Tools

Vivado

Questa

Job description

Role: Principal FPGA Design Engineer

Location: Oxfordshire

Package: £80k - £120k + Bonus + Generous Benefits

About the Business:

We are partnering with a pioneering UK technology innovator developing next-generation medical device technologies. Operating globally, they combine hardware, custom silicon, and complex data processing to transform global healthcare and scientific research.

Role Overview:

A hands-on technical leadership and mentorship position, owning the architecture and delivery of high-throughput FPGA subsystems. You will drive designs across the full lifecycle - from initial requirements through RTL implementation, custom-ASIC bring-up, lab validation, and product release.

Key Responsibilities:

• System Architecture: Lead FPGA subsystem architecture for complex data platforms.
• RTL & Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains.
• Optimization: Maximize throughput, power efficiency, resource usage, and timing closure.
• Integration: Collaborate with ASIC, FW, and SW teams to support board bring-up.
• Leadership: Champion CI/CD automation and mentor mid/senior hardware engineers.

What We Need:

• Proven full-lifecycle FPGA design experience (architecture to hardware bring-up).
• Strong SystemVerilog/Verilog skills with AMD/Xilinx toolchains (Vivado/Questa).
• Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging tools.
• Scripting for workflow automation (Python, Tcl, Make).Degree in Electronic Engineering or equivalent industry background.