Senior Embedded Performance Architect

Fractile Ltd.; Greater London; Hybrid; GBP 65,000 - 90,000; Full time

Benefits offered by this job

Equity ownership

Private medical

Pension & holidays

Diversity & inclusion

Job summary

Fractile is seeking an experienced embedded software engineer to join our UK team, building high‑performance ML accelerators. You will implement and optimize kernels in C, with RISC‑V assembly, and influence the runtime and architecture of our processor.

You’ll collaborate across hardware, software, ML, and firmware domains to translate profiling data into real gains, validate designs with microbenchmarks, and drive end‑to‑end performance improvements in a tight loop.

Qualifications

• Proven deeply embedded software experience.
• Strong performance instincts and low-level reasoning.
• Excellent C and assembly programming, preferably for RISC‑V.
• 3+ years of industry experience in relevant field.

Responsibilities

• Write and optimise performance-critical ML kernels in C, with assembly for critical paths.
• Develop low-level control paths: scheduling, synchronization, data movement.
• Create validation workloads and microbenchmarks to validate hardware behaviour.
• Profile and benchmark to ensure repeatable performance gains.
• Collaborate with simulation, hardware, ML, compiler, firmware, and runtime teams to apply profiling insights.

Skills

Embedded software

Performance optimization

C programming

RISC-V assembly

Team collaboration

Systems architecture

Education

Degree in CS/EE/Math/Physics

Tools

RISC-V toolchain

Simulation tooling

Job description

Fractile is seeking an experienced embedded software engineer to join our UK team, building high‑performance ML accelerators. You will implement and optimize kernels in C, with RISC‑V assembly, and influence the runtime and architecture of our processor.

You’ll collaborate across hardware, software, ML, and firmware domains to translate profiling data into real gains, validate designs with microbenchmarks, and drive end‑to‑end performance improvements in a tight loop.