Senior Digital Verification Engineer

Jobtailor; Glasgow; On-site; GBP 60,000 - 90,000; Full time

Job summary

Jobtailor is seeking a senior verification engineer to verify complex digital hardware architectures and lead verification strategy across the product lifecycle.

Requirements include strong SystemVerilog/UVM experience, constrained random verification, and coverage-driven verification with debugging proficiency. Knowledge of formal verification is a plus, and the role emphasizes mentoring and technical excellence.

Qualifications

• BSc. or MSc. in Electronics or Electrical Engineering.
• Hands-on SystemVerilog for testbench development and verification.
• Expertise in UVM with components, sequences, drivers, monitors, and scoreboards.
• Strong knowledge of constrained random verification techniques.
• Experience with metrics-driven verification, functional coverage and planning.
• Ability to write SystemVerilog Assertions (SVA).
• Proven track record achieving coverage closure across functional/code coverage.
• Experience analysing coverage results and refining test strategies.
• Strong debugging skills in simulations and complex verification environments.
• Knowledge of formal verification methods is advantageous.

Responsibilities

• Verify the functional behaviour of complex digital hardware architectures.
• Create, review, and maintain verification plans and track verification progress.
• Specify and develop verification strategies, tests, and environments for security features and hardware co-processors.
• Work with emerging verification methodologies and introduce them into existing verification flows.
• Mentor junior team members in best practices.
• Drive technical excellence and consistency across teams.
• Contribute across the full product lifecycle, from requirements capture and architectural definition through development and verification to test-chip and silicon validation.

Education

BSc. or MSc. in Electronics or Electrical Engineering

Tools

SystemVerilog

UVM

Constrained Random Verification

SystemVerilog Assertions

Formal Verification Methods

Debugging Skills

Metrics-Driven Verification

Job description

• Verify the functional behaviour of complex digital hardware architectures
• Create, review, and maintain verification plans and track verification progress
• Specify and develop verification strategies, tests, and environments for security features and hardware co-processors
• Work with emerging verification methodologies and introduce them into existing verification flows
• Mentor junior team members in best practices
• Drive technical excellence and consistency across teams
• Contribute across the full product lifecycle, from requirements capture and architectural definition through development and verification to test-chip and silicon validation

Requirements

• BSc. or MSc. degree in Electronics or Electrical Engineering
• Strong hands-on experience with SystemVerilog for testbench development and verification
• Proven expertise in UVM, including component creation, sequences, drivers, monitors, and scoreboards
• Solid understanding and practical use of Constrained Random Verification techniques
• Experience with Metrics-Driven Verification, including functional coverage and verification planning
• Ability to write SystemVerilog Assertions (SVA) for protocol and design checking
• Demonstrated success in achieving coverage closure across functional and code coverage metrics
• Experience analysing coverage results and refining test strategies to close gaps
• Strong debugging skills across simulations and complex verification environments
• Knowledge of Formal Verification methods would be advantageous

Core Competencies

Demonstrates expertise in SystemVerilog and UVM for developing and verifying complex digital hardware architectures, while effectively mentoring team members and driving technical excellence throughout the product lifecycle.

Highest-signal resume keywords

• SystemVerilog Testbench Development
• UVM Component Creation
• Constrained Random Verification Techniques
• Metrics-Driven Verification
• SystemVerilog Assertions

ATS Optimization Keywords

Hard Skills

• SystemVerilog
• UVM
• Constrained Random Verification
• Metrics-Driven Verification
• SystemVerilog Assertions
• Coverage Closure
• Debugging Skills
• Formal Verification Methods

Soft Skills

• Mentoring
• Technical Excellence
• Collaboration

Certifications & Qualifications

• BSc. or MSc. Degree in Electronics or Electrical Engineering

Industry Keywords

• Digital Hardware Architectures
• Verification Plans
• Verification Strategies
• Test-Chip Validation
• Silicon Validation