Senior Design Verification Engineer

JR United Kingdom; Stevenage; On-site; GBP 40,000 - 70,000; Full time

Job summary

Join a leading company at the forefront of the RISC-V revolution as a Verification Engineer. You will be tasked with developing verification infrastructure, defining strategies, and collaborating with various teams to ensure high product quality. This innovative role offers diverse challenges and excellent benefits.

Qualifications

• Proficiency in verification methodologies and SystemVerilog.
• Experience with RISC-V architectures preferred.
• Ability to work with design teams and manage verification metrics.

Responsibilities

• Develop and maintain verification infrastructure.
• Define verification strategies and ensure product quality.
• Manage functional and code coverage metrics.

Skills

SystemVerilog

UVM

Verification methodologies

Debugging

Job description

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Job Views:

4

Posted:

31.05.2025

Expiry Date:

15.07.2025

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Job Description:

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive.

Flat structure with a highly diverse workload and excellent benefits.

Responsibilities:

• Develop and maintain verification infrastructure in collaboration with design teams and external partners.
• Define and implement detailed verification strategies and architectures to ensure product quality and performance.
• Manage functional and code coverage metrics to track and report progress.
• Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

• Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
• A solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.
• Proven ability to work effectively with design teams and external partners to achieve project goals.