Senior DDR Validation Engineer | MRL Consulting

MRL Consulting Group | Global Niche Technology Recruitment; Farnborough; On-site; GBP 60,000 - 90,000; Full time

Job summary

MRL Consulting Group | Global Niche Technology Recruitment in Farnborough is seeking a Senior DDR Validation Engineer to support the development and validation of advanced modem platforms and satellite communication systems.

You will validate DDR interfaces, run plans, and debug issues while collaborating with cross-functional teams to deliver robust, production-ready solutions. Proficiency in Python/C/C++, FPGA bring-up and lab equipment is essential.

Qualifications

• 5+ years' experience in DDR validation, FPGA development or high‑speed digital systems.
• Strong knowledge of DDR3/DDR4, JEDEC standards and memory controller architecture.
• Experience with FPGA bring‑up, Python, C/C++, Git and automated regression frameworks.
• Hands‑on experience using lab equipment such as oscilloscopes and JTAG debuggers.
• Excellent analytical, debugging and communication skills.

Responsibilities

• Validate DDR3/DDR4 interfaces and perform system bring-up.
• Develop and execute DDR validation plans, including timing, voltage, frequency and temperature margin analysis.
• Debug memory training, calibration and initialization issues.
• Support FPGA development and hardware/software co-validation.
• Validate high-speed interfaces including DDR, PCIe and USB.
• Perform signal integrity analysis and automate testing using Python and C/C++.
• Collaborate with cross-functional engineering teams to deliver robust, production-ready solutions.

Skills

DDR3/DDR4

JEDEC standards

Memory controller architecture

FPGA bring-up

Python

C/C++

Git

Automated regression

Oscilloscopes

JTAG debuggers

Analytical skills

Debugging

Communication

Education

Bachelor's degree in Electrical Engineering, Computer Engineering or related discipline

Tools

Oscilloscopes

JTAG debuggers

Job description

We are recruiting on behalf of an innovative technology company for an experienced Senior DDR Validation Engineer to support the development and validation of advanced modem platforms and satellite communication systems.

Key Responsibilities

• Validate DDR3/DDR4 interfaces and perform system bring-up.
• Develop and execute DDR validation plans, including timing, voltage, frequency and temperature margin analysis.
• Debug memory training, calibration and initialization issues.
• Support FPGA development and hardware/software co-validation.
• Validate high-speed interfaces including DDR, PCIe and USB.
• Perform signal integrity analysis and automate testing using Python and C/C++.
• Collaborate with cross-functional engineering teams to deliver robust, production-ready solutions.

Requirements

• Degree in Electrical Engineering, Computer Engineering or a related discipline.
• 5+ years' experience in DDR validation, FPGA development or high-speed digital systems.
• Strong knowledge of DDR3/DDR4, JEDEC standards and memory controller architecture.
• Experience with FPGA bring-up, Python, C/C++, Git and automated regression frameworks.
• Hands-on experience using lab equipment such as oscilloscopes and JTAG debuggers.
• Excellent analytical, debugging and communication skills.

This is an excellent opportunity to join a cutting-edge engineering environment, working on advanced communications technology alongside multidisciplinary teams.