Senior CPU Physical Design Engineer (HPC) - Cambridge

European Tech Recruit; Cambridge; On-site; GBP 90,000 - 120,000; Full time

Job summary

European Tech Recruit is partnering with a global leader in semiconductor innovation to hire a Senior/Staff CPU Physical Design Engineer in Cambridge, UK. The role owns block-level physical implementation for next-generation CPU cores for high-performance compute platforms.

Key responsibilities include RTL-to-GDS, timing closure across modes, and collaboration with RTL, architecture, CAD, and post-silicon teams to improve PPA. Cambridge onsite opportunity.

Qualifications

• Strong experience in physical design — synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff.
• Solid understanding of STA and timing closure methodologies, including PPA trade-offs.
• Hands-on experience with industry-standard EDA tools — Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, or equivalent.
• Scripting experience in TCL, Python, or Perl.
• Experience on CPU cores, advanced nodes (7nm and below), or low-power design techniques advantageous.

Responsibilities

• Own or contribute to CPU block implementation from RTL/netlist to GDS.
• Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.
• Debug and resolve complex implementation issues across timing, congestion, clocking, IR drop, power integrity, EM, and DRC/LVS.
• Collaborate with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve design quality and PPA.
• Develop and enhance physical design flows, automation, and methodologies.

Skills

Physical design

Timing closure

Scripting (TCL/Python/Perl)

Tools

Genus

Innovus

Fusion Compiler

PrimeTime

Tempus

Voltus

RedHawk

Job description

European Tech Recruit is partnering with a global leader in semiconductor innovation to hire a Senior/Staff CPU Physical Design Engineer in Cambridge, UK. The role owns block-level physical implementation for next-generation CPU cores for high-performance compute platforms.

Key responsibilities include RTL-to-GDS, timing closure across modes, and collaboration with RTL, architecture, CAD, and post-silicon teams to improve PPA. Cambridge onsite opportunity.