Senior CPU Performance Architect - Microarchitecture

European Tech Recruit; Cambridge; On-site; GBP 100,000 - 140,000; Full time

Job summary

European Tech Recruit is seeking a Senior CPU HW Performance Architect for a role in Cambridge. You will shape the next generation of CPU microarchitecture and work with hardware and software teams to influence performance, power and area decisions.

The ideal candidate has deep CPU design expertise, cycle-accurate modelling, and hands-on experience with simulators, plus strong C++ and Python programming.

Qualifications

• BS/MS in Computer Science, Computer Engineering, Electrical Engineering or a related discipline, with significant relevant industry experience, or a PhD.
• Strong understanding of CPU microarchitecture, including fetch/decode, branch prediction, rename/dispatch, out-of-order execution, execution units, load/store, prefetching and memory hierarchy.
• Good understanding of performance, power and area trade-offs in high-performance CPU design.
• Strong software engineering and performance profiling skills.
• Programming experience with modern C++ and Python.
• Strong analytical and debugging ability.

Responsibilities

• Define next-generation CPU microarchitecture and high-level specifications in collaboration with hardware and software teams.
• Build and refine cycle-accurate and functional simulators to evaluate new microarchitectural concepts.
• Propose innovative CPU microarchitecture features and analyse their impact on performance, power and area.
• Profile workloads, identify bottlenecks and perform sensitivity analysis to guide CPU optimisation.
• Work closely with architecture, hardware, software and performance engineering teams.

Skills

CPU microarchitecture

Performance profiling

C++

Python

Debugging

Education

BS/MS in CS/CE/EE or PhD

Job description

European Tech Recruit is seeking a Senior CPU HW Performance Architect for a role in Cambridge. You will shape the next generation of CPU microarchitecture and work with hardware and software teams to influence performance, power and area decisions.

The ideal candidate has deep CPU design expertise, cycle-accurate modelling, and hands-on experience with simulators, plus strong C++ and Python programming.