Senior CPU Compiler Performance Engineer (HW-SW Co-Design)

NVIDIA Corporation; Cambridge; On-site; GBP 90,000 - 140,000; Full time

Job summary

NVIDIA Corporation in Cambridge seeks a senior CPU compiler performance engineer to design and optimize compiler and hardware software for AI and HPC workloads across NVIDIA Data Centre platforms.

You will work with a distributed team to improve CPU compiler toolchains, analyze AI workloads, contribute optimizations, and collaborate with upstream projects in a role that blends software and hardware co-design with challenging performance targets.

Qualifications

• 8+ years of compiler development or related projects.
• Hands-on C++ programming and low-level performance analysis.
• Knowledge of front-ends or compiler optimisation and code generation modules.

Responsibilities

• Collaborate with a distributed partner organisation to understand, modify and improve CPU Compiler SW at NVIDIA.
• Analyse AI workloads to champion improvements in hardware and compiler toolchains for hardware-software co-design.
• Contribute new features and optimisation techniques targeting NVIDIA CPUs in upstream and open source communities.
• Develop compiler software optimized for performance across NVIDIA compute platforms.
• Join a team central to AI, HPC, and data centre technologies and drive compute innovations.
• Contribute to next-generation compute through cutting-edge compiler techniques.

Skills

C++

CPU architectures

Compiler development

Education

BS/MS in Computer Science or Computer Engineering

Tools

GCC

LLVM

MLIR

Job description

NVIDIA Corporation in Cambridge seeks a senior CPU compiler performance engineer to design and optimize compiler and hardware software for AI and HPC workloads across NVIDIA Data Centre platforms.

You will work with a distributed team to improve CPU compiler toolchains, analyze AI workloads, contribute optimizations, and collaborate with upstream projects in a role that blends software and hardware co-design with challenging performance targets.