Senior ASIC Architect — Probabilistic Compute Processor

Redline Group Ltd

Oxford

On-site

GBP 110,000 - 160,000

Full time

6 days ago
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Job summary

Redline Group Ltd in Oxford is seeking an experienced ASIC Architect to own the end-to-end architecture of a cutting-edge probabilistic computing processor, from algorithm and ISA definition through tape-out and silicon bring-up.

You will define system architecture, ISA, and dataflow models, perform HW/SW co-design, and build simulations to guide architectural decisions. The role requires strong RTL expertise and experience with industry tool flows.

Qualifications

  • Proven architectural ownership of at least one ASIC taken to tape-out.
  • Strong experience in performance modelling, simulation and architectural trade-off analysis.
  • Hands-on RTL design knowledge and verification strategy development.
  • Experience with industry-standard semiconductor tool flows (Synopsys, Cadence, Siemens).
  • Ability to define hardware/software interfaces and collaborate with firmware teams.

Responsibilities

  • Own the end-to-end ASIC architecture from algorithm to tape-out.
  • Define system and ISA architecture and dataflow models.
  • Perform HW/SW co-design and analyze programmability and host requirements.
  • Build functional simulations and performance models to guide decisions.
  • Conduct timing, power and area trade-offs with design teams.
  • Define microarchitecture details, including memory and interfaces.
  • Lead internal IP development and evaluate external IP.
  • Guide designs through verification, sign-off and silicon bring-up.

Skills

ASIC architecture
Performance modelling
RTL design
C++/Python
Firmware interfaces

Tools

Synopsys Cadence
Siemens EDA
Python

Job description

Redline Group Ltd in Oxford is seeking an experienced ASIC Architect to own the end-to-end architecture of a cutting-edge probabilistic computing processor, from algorithm and ISA definition through tape-out and silicon bring-up.

You will define system architecture, ISA, and dataflow models, perform HW/SW co-design, and build simulations to guide architectural decisions. The role requires strong RTL expertise and experience with industry tool flows.

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