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European Tech Recruit in Cambridge is seeking a highly skilled GPU architect to define and develop cycle-accurate models of GPU subsystems, including shader cores, memory hierarchy and interconnect, for next generation SoCs. You will work with RTL, DV, driver and compiler teams, drive architectural tradeoffs, and contribute to performance, power and area analyses through simulation and profiling.
Strong background in graphics/compute architectures, and proficiency in C/C++, SystemC or Python,
Our client is a global fabless semiconductor company enabling nearly 2 billion connected devices a year. They are a market leader in developing innovative systems on chip (SoC) for mobile devices, home entertainment, connectivity and IoT products. As a leader in SoC design, the company's GPU IP team is focused on industry leading, feature rich and PPA competitive GFX IP optimisation, customisation and development, deployed across flagship and mainstream mobile SoC as well as adjacent markets including laptop, IoT, AI, VR/AR and automotive.
The team is growing across Architecture, Driver, Compiler, Performance, Power and Model disciplines at their Cambridge site.
Please note - this role is 100% onsite in the Cambridge area
You will define and develop best in class GPU architecture and performance and power models for next generation SoCs, building and maintaining cycle accurate, performance and functional models of GPU subsystems such as shader cores, fixed function units, memory hierarchy and interconnect. Using modelling and profiling, you will explore architectural tradeoffs across performance, power and area to guide micro-architecture decisions, and analyse workloads including games, graphics benchmarks, GPU compute and AI/ML kernels through simulation and hardware profiling to identify bottlenecks and optimisation opportunities.
You will collaborate closely with model, RTL, DV, driver, compiler and performance teams to ensure architectural intent is correctly implemented, verified and tuned, and provide architectural input to compiler, driver and runtime teams to maximise utilisation of the GPU hardware.
The role also involves developing methodologies, tools and automation flows for GPU performance estimation, capacity planning and regression analysis, leading debug and root cause analysis of performance, power and bandwidth issues seen in models, emulation and silicon, and driving cross team technical discussions that influence the roadmap for next generation GPUs.
Experience with mobile or low power GPU design and power/performance tradeoff analysis would be an advantage, along with a background in compiler, driver or runtime optimisation for GPUs or accelerators, familiarity with ML/AI workloads and DNN operators and their mapping onto GPU or accelerator architectures, and experience collaborating with silicon implementation, physical design and DV teams on performance and power sign off.
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