Principal Engineer – STA / Constraints Sign-Off Engineer

Aion Silicon Ltd; West of England; On-site; GBP 110,000 - 150,000; Full time

Job summary

Aion Silicon Ltd seeks a highly experienced Principal STA / Constraints Sign-Off Engineer to lead timing signoff methodology development for advanced-node SoC and IP designs. You will drive execution, signoff closure, and automation while collaborating with Architecture, RTL, Verification, DFT, and PD teams to ensure top-tier PPA performance.

The role demands hands-on leadership, deep STA expertise, and a track record of delivering tape-outs with robust timing convergence.

Qualifications

• 12+ years of experience in STA, timing signoff, and ASIC/SoC implementation.
• Deep expertise in SDC constraints, MMMC signoff environments, and closure methodologies.
• Strong scripting skills in Tcl, Python, or Perl for automation and flow development.
• Excellent leadership, debugging, analytical, and cross-functional collaboration skills.

Responsibilities

• Own and drive SoC/IP/blocks timing signoff methodologies across advanced tech nodes.
• Develop, review, and validate SDC constraints, timing exceptions, and signoff environments.
• Lead setup, hold, SI, OCV/AOCV/POCV, and timing closure activities through final signoff.
• Drive timing correlation across synthesis, implementation, extraction, and signoff flows.
• Support ECO closure, low-power timing analysis, and cross-functional signoff activities.
• Develop automation scripts, methodology documentation, training materials, and best practices.
• Collaborate with RTL, Physical Design, DFT, CAD, Verification, and IP teams to achieve timing convergence.

Skills

STA

Timing signoff

ASIC/SoC implementation

Scripting (Tcl/Python/Perl)

Education

BS/MS in Electrical Engineering

Tools

PrimeTime

ICCs/ICC2

Fusion Compiler

StarRC

ICV

Tempus

Innovus

Voltus

Job description

We are seeking a highly motivated Principal STA / Constraints Sign-Off Engineer to lead timing signoff and constraint methodology development for advanced-node SoC and IP designs. The ideal candidate will have deep expertise in STA, timing constraints, signoff closure, and methodology automation, enabling successful tape-outs with best-in-class quality, performance, power, and area (PPA).

This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, RTL, Verification, DFT and PD team collaboration.

Key Responsibilities

• Own and drive SoC/IP/blocks timing signoff methodologies across advanced technology nodes.
• Develop, review, and validate SDC constraints, timing exceptions, and MMMC signoff environments.
• Lead setup, hold, SI, OCV/AOCV/POCV, and timing closure activities through final signoff.
• Drive timing correlation across synthesis, implementation, extraction, and signoff flows.
• Support ECO closure, low-power timing analysis, and cross-functional signoff activities.
• Develop automation scripts, methodology documentation, training materials, and best practices.
• Collaborate closely with RTL, Physical Design, DFT, CAD, Verification, and IP teams to achieve timing convergence.

Required / Preferred Qualifications

• BS/MS in Electrical Engineering or related field with 12+ years of experience in STA, timing signoff, and ASIC/SoC implementation.
• Strong hands-on expertise in PrimeTime, SDC development, MMMC analysis, timing closure, OCV/AOCV/POCV, crosstalk, and ECO methodologies.
• Good understanding of ASIC implementation flows, libraries, memories, PDKs, and advanced-node signoff requirements.
• Strong scripting skills in Tcl, Python, or Perl for flow automation and methodology development.
• Excellent debugging, analytical, communication, and technical leadership skills.
• Experience with advanced-node technologies (7nm/5nm/3nm and below).
• Knowledge of UPF, low-power design, EMIR, and thermal signoff flows.
• Familiarity with high-speed protocols such as PCIe, DDR, UCIE,ABB, PLLs and all latest IPs.
• Experience driving methodology improvements and mentoring engineering teams.

Tools Required:

• Synopsys: PrimeTime (PT/PT-SI/PT-PX), ICC2/Fusion Compiler, StarRC, and ICV for STA, signoff, implementation, extraction, and physical verification.
• Cadence: Tempus, Innovus, and Voltus for timing analysis, physical implementation, and power integrity signoff.
• Scripting: Strong proficiency in Tcl, Python, and Perl for automation, methodology development, and reporting.