Principal Analog IC Design Engineer (Low-Power MCU IP)

Microchip Technology Inc. (China); Cambourne; Vor Ort; GBP 90.000 - 120.000; Vollzeit

Zusammenfassung

Microchip Technology Inc. is seeking a Principal Analog IC Design Engineer to join the Analog IP development group.

The candidate will lead design, simulation, and validation of core analog IPs in a high-performance microcontroller environment, coordinating with system and digital teams. You will define layout floorplans, guide layout designers, and perform IC bench evaluation while using Cadence tools and EDA environments.

Qualifikationen

• Design experience with deep sub-micron process focusing on Micro-controller Peripheral Architectures
• Solid fundamentals of transistor level analog ICs and device physics
• MSEE with >8 years of design experience
• Hands-on analog module design experience (e.g., Ultra Low Power Front End, Power Management)
• Knowledge of Cadence tools and EDA design environment
• Self-motivated with ownership of solutions
• Knowledge of Microcontroller Architecture and SoC verification preferred
• Strong communication and teamwork skills
• Experience in IC bench evaluation and validation preferred
• Interpersonal skills for cross-functional work

Aufgaben

• Lead design and simulation of various analog blocks
• Define layout floorplans and guide layout designers
• IC bench evaluation and validation
• Support technical issues and design documentation
• Analog design using Cadence tools
• Collaborate with other teams to bring up new products
• Work with system and digital teams

Kenntnisse

Strong communication

Teamwork

Self-motivated

Microcontroller architecture

SoC verification

Ausbildung

MSEE

Tools

Cadence

EDA tools

Jobbeschreibung

Microchip Technology Inc. is seeking a Principal Analog IC Design Engineer to join the Analog IP development group.

The candidate will lead design, simulation, and validation of core analog IPs in a high-performance microcontroller environment, coordinating with system and digital teams. You will define layout floorplans, guide layout designers, and perform IC bench evaluation while using Cadence tools and EDA environments.