Lead Physical Design Engineer

NIF; Greater London; Hybrid; GBP 120,000 - 190,000; Full time

Benefits offered by this job

Equity & Ownership

Private Medical, Dental and Vision

Contributory Pension

25 Days holiday plus bank holidays and

Job summary

Fractile is seeking a highly skilled Senior/Principal Physical Design Engineer to drive end-to-end ASIC/SoC implementation, from floorplanning to sign-off, across cross-functional teams. The role emphasizes performance, power and area optimization, with collaboration between RTL, verification, and process technology groups.

Ideal candidates bring 10+ years in physical design for advanced nodes, strong EDA tool proficiency, and experience with power integrity, DFT integration, and HPC/AI

Qualifications

• Bachelor's, Master's or PhD in Electrical or Computer Engineering.
• 10+ years of physical design experience for advanced nodes (e.g., 7nm/5nm+).
• Strong proficiency with place & route, STA, and sign-off flows.
• CMOS knowledge with power integrity and design-for-test awareness.

Responsibilities

• Drive physical implementation of ASIC/SoC designs: floorplanning, placement, CTS, routing, sign-off.
• Work on synthesis, timing analysis, and optimization to improve PPA.
• Perform power planning, IR drop, electromigration, and low-power techniques.
• Ensure DRC and LVS and other V&V checks are met.
• Collaborate with DFT to integrate test structures into layouts.
• Develop flows using Cadence Innovus, Fusion Compiler, Calibre and related tools.
• Interface with foundries and process engineers for manufacturability and yield.
• Work with RTL/architecture teams for physical-aware design feasibility.

Skills

Problem-solving

Communication

Teamwork

Collaboration with RTL/Architecture

AI accelerators experience

Education

Bachelor's/Master's/PhD in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Mentor Calibre

Python scripting

TCL scripting

Job description

Lead Physical Design Engineer

About Fractile

Fractile was founded in 2022 on the bet that, eventually, the world's most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically reinvent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next‑generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign‑off, including opportunities for full‑chip ownership. You will collaborate with cross‑functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign‑off, with potential responsibility for full‑chip execution.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low‑power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design‑for‑test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical‑aware RTL design.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor' Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign‑off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low‑power design methodologies, power optimisation techniques, and multi‑power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem‑solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high‑performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows

What We Offer

• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
• Equity & Ownership: meaningful equity so everyone shares in the value creation.
• Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
• Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.

Fractile is seeking to increase the clock speed of global progress, one chip at a time. We've recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!

Export controls

Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.