GPU Top-Level Physical Design Lead

Lex; Cambridge; On-site; GBP 90,000 - 120,000; Full time

Job summary

Apple in Cambridge is seeking a GPU Top Level Physical Design engineer to collaborate with FE to translate RTL into efficient physical design. You will lead PD efforts, establish guidelines, and drive top-level place-and-route integration with cross-functional teams.

The role requires hands-on PD work on large-scale GPU blocks, with emphasis on clock/power distribution, floorplanning, and IP integration, to ensure high performance and power efficiency.

Qualifications

• Minimum: BSc/MSc in Electrical Engineering (EE) with relevant experience.
• Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Experience with IP integration from internal/external vendors is a plus.

Responsibilities

• Collaborate with FE team to understand RTL and drive physical design early in the design cycle.
• Drive PD methodologies, checklists and best practices for top-level integration.
• Be the focal point for place-and-route at the top level and communicate PD needs across cross-functional teams.

Skills

ASIC integration

Floorplanning

Clock distribution

Power distribution

Global signal planning

I/O planning

Hard IP integration

Top-level PD experience

Education

BSc/MSc in EE

Tools

Floorplanning tools

P&R flows

Physical Design Verification

Global timing verification

Job description

Apple in Cambridge is seeking a GPU Top Level Physical Design engineer to collaborate with FE to translate RTL into efficient physical design. You will lead PD efforts, establish guidelines, and drive top-level place-and-route integration with cross-functional teams.

The role requires hands-on PD work on large-scale GPU blocks, with emphasis on clock/power distribution, floorplanning, and IP integration, to ensure high performance and power efficiency.