Early Career - GPU Top Level Physical Design Engineer

Lex; Cambridge; On-site; GBP 90,000 - 120,000; Full time

Job summary

Apple in Cambridge is seeking a GPU Top Level Physical Design engineer to collaborate with FE to translate RTL into efficient physical design. You will lead PD efforts, establish guidelines, and drive top-level place-and-route integration with cross-functional teams.

The role requires hands-on PD work on large-scale GPU blocks, with emphasis on clock/power distribution, floorplanning, and IP integration, to ensure high performance and power efficiency.

Qualifications

• Minimum: BSc/MSc in Electrical Engineering (EE) with relevant experience.
• Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Experience with IP integration from internal/external vendors is a plus.

Responsibilities

• Collaborate with FE team to understand RTL and drive physical design early in the design cycle.
• Drive PD methodologies, checklists and best practices for top-level integration.
• Be the focal point for place-and-route at the top level and communicate PD needs across cross-functional teams.

Skills

ASIC integration

Floorplanning

Clock distribution

Power distribution

Global signal planning

I/O planning

Hard IP integration

Top-level PD experience

Education

BSc/MSc in EE

Tools

Floorplanning tools

P&R flows

Physical Design Verification

Global timing verification

Job description

Summary

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU. You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.

Description

As a GPU Top Level Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the physical design team, as you develop methodologies and “best known methods” that will enable best-in-class GPU design. You will develop PD guidelines and checklists, drive execution, and supervise progress. Be the focal point for place and route integration at the top level. You will need to communicate and drive the needs of PD with cross-functional teams that will enable achieving the goals of the back‑end design for the project.

Minimum Qualifications

• Minimum of BSc/MSc in EE and some relevant experience.
• Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.

Preferred Qualifications

• Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
• Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
• Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
• Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs.
• Understanding of GPU architecture and design units.
• Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows.

At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more

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Role Number: 200645609-1251