FPGA Hardware Engineer- World-Leading Global Market Maker

Quality Control Specialist - Pest Control; London; On-site; GBP 65,000 - 90,000; Full time

Job summary

A leading company in trading technology is seeking FPGA Hardware Engineers to design and implement ultra-low-latency hardware solutions for financial trading systems. Candidates should have strong FPGA design experience, excellent problem-solving skills, and a Bachelor's degree in a relevant field.

Qualifications

• Minimum 2 years experience in ASIC or FPGA design life cycle.
• Experience working in Verilog, System Verilog, and either Python or C++.
• Ability to work in a Linux environment.

Responsibilities

• Design ultra-low-latency, FPGA-based custom financial trading systems.
• Performance analysis and optimization of existing RTL designs.
• Work closely with cross-functional teams.

Skills

FPGA design flow

Problem-solving

Research skills

Education

Bachelors Degree in Computer Engineering, Computer Science, or related

Job description

FPGA Engineers at this award-winning multi-strategy hedge fund are responsible for the research, design and implementation of FPGA solutions for their ultra-low-latency trading systems. Accelerating trading decisions close to theoretical limits and partnering with both technologists and traders, they provide hardware solutions in areas such as fast networking, high-performance compute, and real-time acceleration.

The FPGA team is small and highly experienced. They're constantly driving to identify ways to become more productive, and are seeking FPGA Hardware Engineers who can help build the next generation of cutting-edge, ultra-low-latency hardware solutions.

Key Responsibilities:

• Work as part of a team on the design and implementation of proprietary hardware trading systems from concept to production.
• Design ultra-low-latency, high-throughput, FPGA-based custom financial trading systems to accelerate algorithmic trade signal generation and order execution.
• Accelerate network infrastructure and trading system components with high-speed FPGA designs.
• Performance analysis and optimization of existing RTL designs.
• Investigate the latency, throughput and capacity of emerging FPGA technologies.
• Work closely with cross-functional teams, including Quantitative Research, Engineering, and Traders.

Skill Set Requirements:

• Minimum 2 years experience in the full ASIC or FPGA design life cycle, including hardware architecture, RTL coding, simulation, verification, system integration, and testing.
• Experience working in Verilog, System Verilog, and either Python or C++.
• Strong working knowledge of FPGA design flow or physical design.
• Ability to work in a Linux environment.
• Exposure to network- and system-level protocols, packet-based data processing, and computer architecture.
• Excellent problem-solving skills, with strengths in conducting research and gathering data.
• Must be adaptable and team-oriented.
• Minimum Bachelors Degree in Computer Engineering, Computer Science, or related.

Financial experience is not required.

Contact
If this sounds like you, or you'd like more information, please get in touch:

George Hutchinson-Binks
[e-mail]
([phone]
linkedin.com/in/george-hutchinson-binks-a62a69252