Formal Verification Senior Engineer - Qualcomm, Cambridge, UK

MaC VC; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Job summary

Qualcomm Technologies International Ltd is seeking a verification engineer specializing in Formal Verification for ASIC design. The role involves developing FPV test plans, writing SystemVerilog Assertions, and collaborating with RTL design and DV teams to deliver signed-off results.

The candidate should have 2+ years in ASIC verification, a strong formal-methods background, and excellent communication skills to contribute across global teams.

Qualifications

• Bachelor's degree and 2+ years in ASIC design/verification.
• Master's degree with 1+ year in ASIC design/verification.
• PhD in Science/Engineering accepted with relevant experience.
• Experience with Formal Verification, FPV and related tools is required.

Responsibilities

• Develop FPV test plans and assertion-based testbenches.
• Collaborate with RTL design and DV teams to meet project goals.
• Write SystemVerilog Assertions and debug RTL artefacts.
• Achieve formal sign-off matrices and coverage closure.

Skills

Formal Verification

SystemVerilog Assertions

Proof techniques

Bug-hunting

Communication

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Electronics/Computer Engineering

Tools

JasperGold

VC Formal

DPV

C2RTL

Job description

Company

Qualcomm Technologies International Ltd

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

• Develop deep understanding of 3D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces; Prior knowledge of GPU Architecture is a big plus.
• Hands-on experience in strategizing, brainstorming, and developing Formal Property Verification (FPV) test-plan, developing an assertion-based verification testbench, debugging all RTL artefacts, and achieving formal sign-off matrices is a MUST.
• Collaborate with global GPU RTL design and DV teams to achieve the project goals.
• Required proficiency with industry standard formal tools, hands-on experience writing SystemVerilog Assertions, solving formal proof complexity by applying various abstraction techniques, deep bug-hunting, coverage closure and achieving sign-off.
• Hands-on experience in other formal applications like DPV, C2RTL SEQ, RTL2SEQ, etc. is a plus.
• Strong communication skills, ability to learn, improve, and deliver

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.

Preferred Education Requirements

Bachelors/Masters in Electronics/Computer Engineering

Technical Experience

2+ years of relevant experience in Formal Verification

Keywords

Formal Property Verification (FPV), DPV, C2RTL, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal

• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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