Experienced GPU Top Level Physical Design Engineer

Lex; Greater London; On-site; GBP 90,000 - 170,000; Full time

Job summary

Apple is seeking a Senior ASIC Physical Design Engineer to join its Silicon Technologies group in London.

You will lead full chip integration from netlist to tape-out, collaborating with FE and the physical design teams to deliver high‑performance, power‑efficient GPUs.

The role requires an MSEE or equivalent and deep experience in Floorplanning, Clock & Power distribution, IP integration, and design for yield. Excellent communication and problem‑solving skills are essential.

Qualifications

• MSEE or equivalent is required.
• Deep experience with ASIC integration including Floorplanning, Clock & Power distribution, global signal planning, I/O planning & hard IP integration.

Responsibilities

• Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle.
• Contribute to innovation with the physical design team and develop methodologies and “best known methods” that will enable outstanding GPU design.
• Develop PD guidelines and checklists and drive execution. Be the focal point for place and route integration at the top level.
• Plan short and long‑term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
• Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution.
• If you are a confident problem solver who thrives under pressure to find new, creative solutions, we are excited to hear from you!

Education

MSEE or equivalent

Tools

Floorplanning

P&R flows

Global timing verification

Physical Design Verification Flows

IP integration

Top-level integration

Job description

Summary

Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next‑generation, high‑performance, power‑efficient GPU! You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices!

Description

This role requires a mix of strategic engineering along with hands‑on, technical work, being responsible for implementing complete chip design from netlist to tape‑out and having hands on experience in physical design and large chip integration.

Responsibilities

• Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle.
• Contribute to innovation with the physical design team and develop methodologies and “best known methods” that will enable outstanding GPU design.
• Develop PD guidelines and checklists and drive execution. Be the focal point for place and route integration at the top level
• Plan short and long‑term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
• Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution.
• If you are a confident problem solver who thrives under pressure to find new, creative solutions, we are excited to hear from you!

Minimum Qualifications

• MSEE or equivalent is required.
• Deep experience with all aspects of ASIC integration including Floorplanning, Clock & Power distribution, global signal planning, I/O planning & hard IP integration.

Preferred Qualifications

• Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
• Familiar with hierarchical design approach, top‑down design, budgeting, timing and physical convergence.
• Depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
• Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand‑new technologies.
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
• From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.

At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we’re committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Role Number: 200619403-2114