Senior GPU Top Micro-Architect

APPLE; Greater London; On-site; GBP 95,000 - 160,000; Full time

Job summary

Apple's GPU top design team in London seeks a senior design engineer to drive micro-architecture and RTL across critical IPs, owning the design flow from concept to physical handoff and contributing to GPU-level assembly and integration on-site.

Collaborate across teams to optimize performance, verify CDC/RDC, and mentor junior engineers while delivering robust designs under tight schedules.

Qualifications

• Expertise in logic synthesis and digital design.
• Strong SystemVerilog/VHDL skills and version control proficiency.
• Ability to solve complex problems and work across teams on tight schedules.

Responsibilities

• Develop micro-architecture for owned IP and system-level improvements.
• Design and synthesize IP blocks.
• Design clocking and reset distribution; perform CDC/RDC verification.
• Contribute to GPU top-level assembly and integration.
• Debug and analyze top-level design issues.
• Prepare deliverables for physical design handoff.
• Codeline management across multiple products and chips.
• Review RTL implementations and mentor junior engineers.

Skills

Logic synthesis

SystemVerilog/VHDL

Revision control

Tools

Git

Job description

Summary

Posted: 23 Sept 2025

Role Number: 200622517-2114

Description

The GPU top design team develops micro-architecture and RTL for critical top-level infrastructure IP, and drives micro-architectural improvements across the entire GPU through our holistic system-level perspective. We own complete IP blocks including interconnects, control logic, and clocking/reset distribution. Our unique position working across the full GPU scope enables us to identify optimization opportunities that span multiple units which means our micro-architecture work can influence outside of IP that we own when we identify better system-level solutions. We handle the complete design flow for our IP from concept through physical design handoff, while also contributing to GPU-level assembly and integration.

Responsibilities

• Micro-architecture development (for owned IP and system-level improvements)
• IP design and synthesis (owned blocks)
• Design clocking and reset distribution, perform CDC/RDC verification
• Contribute to GPU top-level assembly/integration
• Debug and analyse top-level design issues
• Prepare deliverables for physical design handoff
• Codeline management, supporting multiple products & chips
• Review RTL implementations and mentor junior engineers

Minimum Qualifications

• Expertise in design including logic synthesis
• Expertise in SystemVerilog/VHDL and proficiency in revision control systems
• Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules

Preferred Qualifications

• Understanding of computer architecture and physical design
• Experience with large-scale SoC or GPU design
• Experience of scripting languages (for example Python/Ruby/Tcl)

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