EDA Database Engineer II — Hybrid

Cadence; Cambridge; Hybrid; GBP 55,508 - 81,127; Full time

Benefits offered by this job

Competitive salary

30 days holiday

Group pension

JobRad

EGYM Wellpass

Lunch vouchers

Volunteer time off

Employee Stock Purchase Plan

Great Place to Work

Job summary

Cadence is seeking a Software Engineer II to join the Innovus/Genus database team within the DDI unit. You will build database infrastructure powering chip-design tools, impacting performance and reliability of Cadence software used by leading semiconductor companies.

This role involves tackling challenging problems in a global, distributed team across Europe, the US and Asia. Hybrid work is available at Munich or Cambridge offices, with focus on C++, Tcl, Linux, and internal toolchains.

Qualifications

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering or related field, or equivalent experience.
• Min 2 years of professional software development in a relevant engineering environment.
• Strong proficiency in C++ with modern standards.
• Understanding of IC design data models and database architecture.

Responsibilities

• Design, develop, and optimise EDA database infrastructure software and APIs.
• Investigate defects and provide robust fixes with root-cause analysis.
• Collaborate with application engineering to profile and improve API performance.
• Reduce database memory footprint for large-scale IC designs.
• Contribute to architectural discussions and design reviews.
• Write clean, well-tested code and documentation to Cadence standards.
• Participate in agile ceremonies as a constructive team member.
• Stay current with EDA, database architecture, and AI-assisted tooling.

Skills

C++ proficiency

Unix/Linux development

DB design concepts

IC design data models

Verilog familiarity

Education

Bachelor’s or Master’s in CS/EE or equivalent

Tools

UNIX/Linux tooling

Job description

Cadence is seeking a Software Engineer II to join the Innovus/Genus database team within the DDI unit. You will build database infrastructure powering chip-design tools, impacting performance and reliability of Cadence software used by leading semiconductor companies.

This role involves tackling challenging problems in a global, distributed team across Europe, the US and Asia. Hybrid work is available at Munich or Cambridge offices, with focus on C++, Tcl, Linux, and internal toolchains.