Application Specific Integrated Circuit Design Engineer

IC Resources; Cardiff; On-site; GBP 60,000 - 80,000; Full time

Job summary

A leading semiconductor company in Cardiff is seeking a Principal Design Engineer to shape technical direction and development culture. You will define digital architectures, develop high-quality RTL, and mentor junior engineers. The ideal candidate will have proven digital IC design expertise and a strong background in AI/ML hardware. This full-time role requires regular on-site presence and offers a chance to work at the forefront of innovation in the semiconductor industry.

Qualifications

• Proven experience in digital IC design.
• Deep understanding of SoC architecture.
• Confident user of Cadence tools and environments.

Responsibilities

• Define digital architectures for AI accelerators.
• Develop synthesizable RTL using Verilog/SystemVerilog.
• Collaborate with verification and physical design teams.
• Lead design reviews and establish methodologies.
• Mentor junior engineers.

Skills

Digital IC design expertise

AI/ML hardware experience

SoC architecture understanding

Mentoring capability

Cadence tools proficiency

Tools

Cadence digital tools

Job description

Application Specific Integrated Circuit Design Engineer

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Business Manager – Semiconductor Division

Principal Design Engineer / Technical Lead

Wales – Commutable from Bristol

Join a pioneering start‑up backed by one of the largest EDA companies globally. This is a rare opportunity to help build a digital design team from the ground up, focused on pushing the boundaries in AI, future compute, and compound semiconductors.

As a Principal Design Engineer, you will play a foundational role in shaping the company’s technical direction, development culture, and working methodologies. You’ll lead the architecture and RTL development of advanced compute silicon, working at the forefront of innovation and with top‑tier industry partners.

Key Responsibilities

• Define digital architectures for AI accelerators, data paths, control logic, and SoC subsystems.
• Develop high‑quality, synthesizable RTL in Verilog/SystemVerilog with performance, power, and area optimization in mind.
• Collaborate cross‑functionally with verification, physical design, and packaging teams to ensure seamless integration.
• Leverage Cadence digital tools for synthesis, STA, and DFT.
• Lead design reviews and help establish design methodologies and best practices.
• Support tape‑out and lab‑based silicon validation.
• Mentor junior engineers and help grow team capabilities.

Requirements

• Proven experience in digital IC design with a strong background in AI/ML hardware, compute, or DSP architectures.
• Deep understanding of SoC architecture, PPA trade‑offs, and modern design flows.
• Confident user of Cadence tools and design environments.
• Prior experience leading or mentoring engineering teams.
• Must have the right to work in the UK and be available on‑site several days per week.

For a confidential discussion, please contact Rachel Mason at IC Resources.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Computer Hardware Manufacturing and Semiconductor Manufacturing

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