DFT Engineer

IC Resources

Cambridge

On-site

GBP 65,000 - 90,000

Full time

2 days ago
Be an early applicant

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

IC Resources is seeking a DFT Engineer in Cambridge to help shape the next generation of high‑performance ASICs. You will be involved across the full silicon lifecycle, from architecture and specification through design, verification, implementation, testing and production.

You will define, implement and verify DFT methodologies, working closely with Design, Verification, Physical Implementation and Product Engineering teams to deliver robust test solutions.

Qualifications

  • Experience in modern ASIC/SoC development flows.
  • Strong knowledge of DFT concepts, test architectures and integration challenges.
  • Experience with ATPG, MBIST, IJTAG and test access standards.
  • Proficient in Tcl scripting; Python scripting is a plus.

Responsibilities

  • Define DFT strategies at chip, subsystem and IP level.
  • Implement structural and functional DFT methodologies across complex ASIC designs.
  • Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure.
  • Verify DFT implementation and debug related issues through the design cycle.
  • Support implementation and sign-off, including timing constraints and power analysis.
  • Collaborate with Physical Design and Verification teams for integration.
  • Support ATPG generation, silicon bring-up and manufacturing test.
  • Mentor and support other engineers in the team.

Skills

ATPG
MBIST
Scan architecture
DFT verification
IJTAG
UPF
Tcl scripting
Python scripting
Clocking & reset
Collaboration

Tools

Siemens Tessent DFT

Job description

Join a Growing ASIC Team Developing Next-Generation Silicon - Cambridge

I'm currently working with an innovative technology company that designs and develops its own silicon in-house. Following the successful delivery of multiple production ASICs, the team is continuing to expand as they develop the next generation of high-performance devices.

This is an excellent opportunity to join a collaborative ASIC team involved throughout the complete silicon development lifecycle - from architecture and specification through design, verification, implementation, manufacturing test and production.

As a DFT Engineer, you'll play a key role in developing robust Design-for-Test solutions for future ASICs, helping ensure high-quality silicon is delivered into volume production while balancing test coverage, implementation complexity and time-to-market.

You'll be responsible for defining, implementing and verifying DFT methodologies across complex SoC and IP designs, working closely with Design, Verification, Physical Implementation and Product Engineering teams.

Responsibilities
  • Define DFT strategies at chip, subsystem and IP level
  • Implement structural and functional DFT methodologies across complex ASIC designs
  • Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure
  • Verify DFT implementation and debug related issues throughout the design cycle
  • Support implementation and sign-off, including timing constraints, timing closure, power analysis and formal equivalence checking
  • Work closely with Physical Design and Verification teams to ensure successful integration
  • Support ATPG generation, silicon bring-up and manufacturing test
  • Mentor and support other engineers within the team
What they're looking for
  • Experience working within modern ASIC or SoC development flows
  • Strong experience with Siemens Tessent DFT tools
  • Good understanding of complex DFT challenges, including clocking, reset architecture and IP integration
  • Experience with:ATPG
  • MBIST
  • Scan architecture
  • DFT verification and simulation debug
  • UPF and low-power verification concepts
  • Good Tcl scripting skills (Python is also beneficial)
  • Collaborative approach with excellent troubleshooting and debugging skills
  • Knowledge of advanced silicon technologies and manufacturing fault models
  • Familiarity with IJTAG / IEEE 1687 and related test access standards
  • Experience supporting vector translation and production bring-up on ATE platforms
  • Previous experience mentoring or coaching other engineers
About You

You'll enjoy solving technically challenging problems, working across multiple engineering disciplines and taking ownership of high-quality DFT implementation from architecture through to production.

You're someone who enjoys collaborating with experienced engineers, sharing knowledge, and contributing to the successful delivery of complex silicon products.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

DFT Engineer - Next-Gen ASICs & Full Lifecycle
DFT Engineer - Next-Gen ASICs & Full Lifecycle

IC Resources • Cambridge

On-site
GBP 65,000 - 90,000
Senior/Principal DFT Engineer
Senior/Principal DFT Engineer

Fractile • Greater London

On-site
GBP 90,000 - 130,000
Equity & Ownership
Private Medical, Dental & Vision
Contributory Pension
+1
DFT Engineer
DFT Engineer

Raspberry Pi Ltd • Cambridge

On-site
AUD 90,000 - 120,000
Employer pension contributions of 8%
Life assurance of 4x base salary
Income protection of 75%
+2
DFT Engineer for Next-Gen ASICs: Test, Sign-off, Mentoring
DFT Engineer for Next-Gen ASICs: Test, Sign-off, Mentoring

Raspberry Pi Ltd • Cambridge

On-site
AUD 90,000 - 120,000
Employer pension contributions of 8%
Life assurance of 4x base salary
Income protection of 75%
+2
DFT Engineer
DFT Engineer

Graphcore • West of England

On-site
GBP 70,000 - 110,000
Flexible working
Generous leave
Pension matching
+7
Senior DFT Engineer for AI Compute Silicon
Senior DFT Engineer for AI Compute Silicon

Graphcore • Cambridge

On-site
GBP 90,000 - 120,000
Flexible working
Private medical insurance
Pension (matched)
+3
Silicon DFT Engineer — Multiple Levels
Silicon DFT Engineer — Multiple Levels

Graphcore • Cambridge

On-site
GBP 90,000 - 120,000
Flexible working
Private medical insurance
Pension (matched)
+3
Silicon DFT Engineer — Multiple Levels
Silicon DFT Engineer — Multiple Levels

Graphcore • Cambridge

On-site
GBP 70,000 - 110,000
Flexible working
Generous leave
Retirement planning support
+5
DFT Silicon Engineer – Flexible Work & Equity
DFT Silicon Engineer – Flexible Work & Equity

Graphcore • Cambridge

On-site
GBP 70,000 - 110,000
Flexible working
Generous leave
Retirement planning support
+5
Senior/Principal DFT Engineer
Senior/Principal DFT Engineer

NIF • Greater London

On-site
GBP 90,000 - 130,000
Competitive salary
Equity
Private health coverage
+3