Design Verification Engineer

JR United Kingdom; Peterborough; On-site; GBP 40,000 - 70,000; Full time

Job summary

A leading company in the engineering sector seeks a Design Verification Engineer in Peterborough. The role involves verifying CPU connectivity, developing test plans, and ensuring functional coverage through rigorous testing methodologies. The successful candidate will leverage UVM and System Verilog to create robust verification solutions while collaborating closely with the development team.

Qualifications

• Experience with design verification methodologies.
• Proficient in writing test plans and test cases.
• Strong debugging skills for test failures.

Responsibilities

• Verify CPU connectivity to IP blocks and run regressions.
• Develop tests for functional and code coverage.
• Provide verification reports as needed.

Skills

CPU connectivity

Test methodologies

Functional verification

Code coverage analysis

Debugging

Verification techniques

Tools

UVM

Verilog/System Verilog

GNU toolchain

C

ASM boot

Job description

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Design Verification Engineer, peterborough

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Client:

ALOIS Solutions

Location:

peterborough, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

8

Posted:

10.06.2025

Expiry Date:

25.07.2025

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Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)

• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems

• Run regressions, debug test failures and file bug report as needed.

• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.

• Provide verification report as needed to show all implemented tests passing on the RTL.

• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases