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Design Verification Engineer

G-Research

London

On-site

GBP 50,000 - 80,000

Full time

3 days ago

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Job summary

A leading firm in quantitative research is seeking a Design Verification Engineer for their London office. The role focuses on technical expertise in formal verification tools, developing complex verification environments based on System Verilog and UVM methodologies while providing support within client methodologies.

Benefits

Highly competitive compensation plus annual discretionary bonus

Lunch provided via Just Eat for Business

35 days’ annual leave

9% company pension contributions

Comprehensive healthcare and life assurance

Qualifications

Extensive experience with large FPGA and ASIC design.
Background in fintech beneficial.
Comfortable writing test plans and creating test benches.

Responsibilities

Developing System Verilog based VMM/UVM test bench environments.
Writing test plans, creating test bench specifications.
Analyzing code coverage plans and implementing constrained-random sequences.

Skills

Knowledge of industry-standard interfaces

Experience with FPGA/ASIC designs

Experience with build tools

Knowledge of QuestaSim environment

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Do you want to tackle the biggest questions in finance with near infinite compute power at your fingertips?

G-Research is a leading quantitative research and technology firm, with offices in London and Dallas.

We are proud to employ some of the best people in their field and to nurture their talent in a dynamic, flexible and highly stimulating culture where world-beating ideas are cultivated and rewarded.

This is a role based in our new Soho Place office – opened in 2023 - in the heart of Central London and home to our Research Lab.

The role

G-Research is seeking a Design Verification Engineer to join our world-class Software Engineering function.

As a Design Verification Engineer, you will provide technical expertise, support and guidance around formal verification tools. Working within our client’s methodology and flows, you will oversee the effective application of formal verification.

You will have excellent knowledge of industry standard interfaces and build tools, and be comfortable writing test plans, creating test benches and analysing code coverage.

Key responsibilities of the role include:

Developing System Verilog based VMM/UVM test bench environments
Developing assertion based formal verification
Developing co-simulation environments to verify between C/C++ models and RTL modules
Writing test plans, creating test bench specifications and analysing code coverage plans
Implementing constrained-random sequences, agents and environments using the UVM methodology
Developing and maintaining complex verification environments using different methodologies, such as UVM and SV

Who are we looking for?

We are looking for an engineer with extensive experience of large FPGA and ASIC design to join our Software Engineering function.

The ideal candidate will have the following skills and experience:

Knowledge of industry-standard interfaces, such as Avalon and AXI
Experience with industry-standard build tools, including version control
Knowledge of QuestaSim environment
Must have extensive experience with large FPGA/ASIC designs
A background in fintech would also be beneficial

Why should you apply?

Highly competitive compensation plus annual discretionary bonus
Lunch provided (via Just Eat for Business) and dedicated barista bar
35 days’ annual leave
9% company pension contributions
Informal dress code and excellent work/life balance
Comprehensive healthcare and life assurance
Monthly company events

Seniority level

Seniority level
Not Applicable

Employment type

Employment type
Full-time

Job function

Job function
Engineering, Information Technology, and Finance
Industries
Capital Markets

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