Design Verification Engineer

JR United Kingdom; Crawley; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading company in the technology sector seeks a Design Verification Engineer for their Crawley office. This role involves verifying CPU connectivity, developing test plans, and ensuring thorough functional verification across various design blocks. The ideal candidate has extensive experience with verification techniques and a strong understanding of programming in C.

Qualifications

• Experience with CPU connectivity verification using ASM boot and C code.
• Skilled in developing test methodologies and test plans.
• Familiarity with verification techniques using UVM and emulators.

Responsibilities

• Verify CPU connectivity to IP blocks and write test cases.
• Run regressions, debug failures, and file bug reports as needed.
• Develop tests to meet coverage requirements based on analysis.

Skills

CPU connectivity verification

Test plan development

Debugging test failures

Functional verification methods

UVM methodologies

C programming

Verilog/SystemVerilog

Tools

GNU toolchain

Job description

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Design Verification Engineer, Crawley, West Sussex

Client: ALOIS Solutions

Location: Crawley, West Sussex, United Kingdom

Job Category: Other

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EU work permit required: Yes

Job Views: 5

Posted: 09.06.2025

Expiry Date: 24.07.2025

Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification, and closing coverage for all the agreed design blocks in the SoCs/Subsystems
• Run regressions, debug test failures, and file bug reports as needed.
• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.
• Provide verification reports as needed to show all implemented tests passing on the RTL.
• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based testcases.