CPU Power-Management Design Engineer

SiFive Inc; Cambridge; On-site; GBP 118,000 - 144,000; Full time

Job summary

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to help design industry-leading CPU and interconnect IP for RISC-V based SOCs. You will work with architecture and design teams to implement core clocking, reset and power-management solutions and improve time-to-market.

The ideal candidate has 3+ years in CPU/SoC clocking and power-management, RTL design in Verilog/SystemVerilog or VHDL, and strong verification collaboration.

Qualifications

• 3+ years of experience in CPU/SoC clocking and power-management logic designs.
• Experience with high-performance energy-efficient CPU/SoC designs.
• Proficiency with RTL design in Verilog/SystemVerilog or VHDL.
• Knowledge of DFT, MBIST, debug and error handling in CPU designs.

Responsibilities

• Define power-management requirements with architecture team.
• Architect, design and implement core clocking, reset and power-management solutions.
• Develop microarchitecture and write specifications; share knowledge via documentation.
• Perform sandbox verification and collaborate on full verification plans.
• Collaborate with physical design to meet frequency, area and power goals.
• Work with software teams to enable and optimize power-management features.

Skills

RTL design

Verilog/SystemVerilog

Power-management

Clocking design

DVFS

DFT/MBIST/Debug

Git/GitHub

Confluence/Jira

Education

BS/MS in EE/CE/CS or related discipline

Tools

Spyglass

AMBA AXI/AHB/APB

AMBA Low Power Interfaces

Job description

SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer you will be part of a team creating highly configurable IP and improving time-to-market by designing hardware with the agility of software development.,

• Work with the architecture team to understand and define power management requirements.
• Architect, design and implement core clocking, reset and power-management solutions.
• Develop microarchitecture and write specifications, ensuring knowledge sharing through clear documentation.
• Perform initial sandbox verification and collaborate with the design-verification team to create and execute thorough verification test plans.
• Work with the physical-implementation team to implement and optimise physical design to meet frequency, area and power goals.
• Collaborate with software teams to enable and optimise power-management features.
• 3+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.
• Experience in high-performance, energy-efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset design, and power management, including: + Reset control and design strategies: clock distribution, dynamic clocking, clock gating, clock boundary crossing strategies. + Power-state definition and management and Power Management Unit (PMU) design. + Dynamic and static power reduction techniques: retention, power-up/down sequencing. + Dynamic voltage and frequency scaling (DVFS) and diode-current mitigation strategies. + Understanding of DFT, MBIST, debug and error handling in CPU designs. + Power-aware simulation.
• Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Good understanding of RTL quality checks such as Lint, CDC, RDC.
• Hands-on experience with Spyglass is a plus.
• Attention to detail and focus on high-quality design.
• Ability to work well with others and belief that engineering is a team sport.
• Knowledge of at least one object-oriented or functional programming language.
• Background of successful CPU or SoC development from architecture through tape-out.
• BS/MS degree in EE, CE, CS or related technical discipline, or equivalent experience., Experience with AMBA Interconnect Protocols (AXI, AHB, APB).
• Experience with AMBA Low Power Protocol Interface (P-channel, Q-channel).
• Experience with Scala/Chisel, Bluespec or other language/DSL for configurable hardware.
• Knowledge of RISC-V architecture.
• Experience with Git, GitHub, Jira, Confluence.
• Position requires successful background and reference checks and proof of right to work in the United States. Eligibility for export-controlled technology access may be required. SiFive is an equal-employment-opportunity employer. SiFive is proud to be an equal-employment-opportunity workplace. All applicants will be required to complete a Form I-9, Employment Eligibility Verification.
• Base Pay Range: $158,760.00-$194,040.00 (depending on location, experience, and skills). In addition to base pay, the role may be eligible for variable/incentive compensation and equity. Comprehensive benefits include healthcare, retirement plans, paid time off, and more.