ASIC Architect

Redline Group - Specialist Recruitment for Technology & Electronics Companies; Oxford; On-site; GBP 90,000 - 130,000; Full time

Job summary

Unknown in Oxford is seeking an experienced ASIC Architect to own the end-to-end architecture of a probabilistic computing processor, guiding from algorithm and ISA definition through tape-out and silicon bring-up.

You will define system architecture and dataflow models, perform HW/SW co-design, and build simulations to inform decisions, with strong emphasis on timing, power and area trade-offs and verification strategy development.

Qualifications

• Proven ownership of an ASIC taken to tape-out.
• Experience with compute accelerators, inference engines or DSP applications.
• Strong modelling, simulation and trade-off analysis using Python, C++ or similar languages.
• Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools.
• Solid understanding of timing, power and area optimisation at the architectural level.
• Experience defining hardware/software interfaces and collaborating with firmware and compiler teams.
• Strong RTL design knowledge and experience defining verification strategies from an architectural perspective.

Responsibilities

• Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out.
• Define system architecture, ISA and dataflow models based on workload requirements.
• Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements.
• Build functional simulations and performance models to guide architectural decisions.
• Conduct timing, power and area trade-off analysis with strong physical design awareness.
• Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements.
• Lead internal IP development and evaluate third-party IP solutions.
• Guide designs through verification, sign-off, tape-out and silicon bring-up.

Skills

Architectural ownership

Performance modelling

RTL design

Python/C++

EDA tool flows

Verification strategy

Tools

Synopsys

Cadence

Siemens EDA

Job description

Great opportunity for an experienced ASIC Architect to join an innovative next-generation computing company and taking ownership of the architecture and development of a cutting-edge probabilistic computing processor. This is a highly influential role where you will lead ASIC architecture from algorithm and ISA definition through to tape-out and silicon bring-up.

Key Responsibilities for the ASIC Architect role based in Oxford:

• Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out.
• Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements.
• Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements.
• Build functional simulations and performance models to guide architectural decisions.
• Conduct timing, power and area trade-off analysis with strong physical design awareness.
• Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements.
• Lead internal IP development and evaluate third-party IP solutions.
• Guide designs through verification, sign-off, tape-out and silicon bring-up.

Key Skills Required for the ASIC Architect role based in Oxford:

• Proven architectural ownership of at least one ASIC taken successfully to tape-out, ideally within compute accelerators, inference engines or DSP applications.
• Strong hands-on experience with performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar languages.
• Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools.
• Solid understanding of timing, power and area optimisation at the architectural level.
• Experience defining hardware/software interfaces and collaborating with firmware and compiler teams.
• Strong RTL design knowledge and experience defining verification strategies from an architectural perspective.

This is a fantastic opportunity to play a pivotal role in developing revolutionary computing technology, influencing product direction and driving innovation from concept through to silicon deployment.