System-Design-Technology Co-Optimization H/F

CEA; Grenoble; Sur place; EUR 40 000 - 60 000; Plein temps

Résumé du poste

A leading research organization is offering an internship in System Design-Technology Co-optimization in Grenoble. The role involves developing methodologies for optimizing chip designs, conducting simulations, and power estimation. Candidates must have graduate-level experience in system architecture and knowledge of relevant programming languages. This 6-month internship offers benefits for accommodation and public transportation.

Prestations

Remuneration during internship

Accommodation in Grenoble

Public transportation benefits

Qualifications

• Experience with system architecture and modeling tools.
• Familiarity with design flows relevant to ASIC.
• Ability to develop SystemC/TLM models.

Responsabilités

• Develop STCO methodology in various technological aspects.
• Conduct Design Space Exploration via system-level simulations.
• Perform power estimation and optimize design efficiency.

Connaissances

System architecture

C/C++ programming

Python programming

SystemC modeling

Hardware Description Languages

Formation

Master's degree or last year of engineering school

Description du poste

Overview

System-Design-Technology Co-optimization H/F | Internship

This internship is dedicated to master students looking for an ambitious research-oriented experience, using state-of-the-art EDA tools offered by major CAD vendors. It targets system-level design and power/integration optimization for chip designs through a System-Design-Technology Co-optimization (STCO) methodology.

Responsibilities

• Participate in the development of an STCO methodology focusing on various technological aspects.
• Conduct Design Space Exploration (DSE) by simulating, at system level, different configurations through changes in system architecture, memory technology, or application, to identify the optimal design.
• Use a virtual prototyping platform based on SystemC simulation with IPs modeled using the TLM standard.
• Develop systemC/TLM models and perform power estimation to optimize design efficiency and performance.
• Apply power estimation techniques based on simulation input data, profiling methodologies, and data from datasheets, literature, or existing designs.
• Carry out RTL-level and back-annotated gate-level simulations and extract switching activity (VCD/FSDB) for detailed power analysis in PrimePower under various workloads.
• Correlate simulation results with datasheet or literature data to verify and improve modeling accuracy.
• Contribute to validating power estimation methodologies for different SoC IPs.

Qualifications

• Graduate-level experience in system architecture; familiarity with Hardware Description Languages and/or SystemC modeling and/or software development (C/C++ and Python).
• Knowledge of the ASIC design flow is a plus and will be reinforced during the internship.
• Master (or engineering school) student in their last year; possibility to base a master’s thesis on internship topics.

Context and Collaboration

The internship is conducted in collaboration with a 3rd-year PhD student and offers opportunities for future PhD positions within the team or department.

Remuneration and Benefits

The student will have a 6-month remunerated stage contract, with benefits for accommodation in Grenoble and public transportation.

Site and Location

Site: Grenoble

Location: Grenoble

Organisation

The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas: defence and security, nuclear energy (fission and fusion), technological research for industry, and fundamental research in physical and life sciences. The LIST institute, part of CEA, focuses on smart digital systems and integrated circuit design across applications such as cybersecurity, IoT, and AI. This internship takes place at the Grenoble site of CEA-List.

Reference

Reference: 2025-38045