Senior RTL Development and UVM Verification Engineer

Secure IC; Rennes, Paris; Sur place; EUR 45 000 - 65 000; Plein temps

Résumé du poste

A technology firm is seeking a senior engineer based in Rennes or Paris. The candidate will work within the Product Quality Engineering Department on the assembly, integration, and validation of complex systems based on embedded RISC-V processors. Responsibilities include developing HDL blocks and verifying RTL code quality. Proficiency in VHDL/Verilog and a strong background in RTL development and ASIC/FPGA environments are essential. Fluency in French and English is required.

Qualifications

• Several professional experiences in RTL development and/or verification.
• Proficiency in VHDL and/or Verilog and/or SystemVerilog.
• Good knowledge of ASIC and FPGA environments.

Responsabilités

• Develop and integrate HDL blocks into complex systems.
• Verify the quality of RTL code.
• Participate in debugging and technical support.

Connaissances

RTL development

VHDL

Verilog

Python scripting

RISC-V CPU knowledge

Collaboration

Description du poste

Permanent contract (CDI), based in Rennes or Paris.

Context

Within the “Product Quality Engineering” Department, you will join a multidisciplinary team of 10 people (processor architecture, RTL verification, FPGA prototyping, software integration).

We develop and validate generic security systems based on embedded RISC-V processors, as well as their derivatives for international customers in the semiconductor field (ASIC and FPGA).

Your role

As a senior engineer, you will be involved in the assembly, integration, and validation of complex systems, in direct collaboration with all R&D teams. You will take ownership of your tasks with a high level of autonomy and will quickly become operational on high-impact projects.

Main missions

• Develop and integrate HDL blocks (VHDL/Verilog, soft IP) into complex systems
• Verify the quality of RTL code (lint, ASIC and FPGA synthesis, RTL reviews)
• Develop and improve test benches (RTL/firmware simulation, FPGA prototyping)
• Define and execute test plans, develop verification scenarios (UVM, RTL simulation)
• Contribute to the improvement of automated processes (Python scripts, automation)
• Write technical documentation (detailed architecture, user manuals)
• Participate in debugging and technical support, in collaboration with software teams and customers.

Education, Experience & Skills

• Several professional experiences in RTL development and/or RTL verification and/or RTL integration
• Proficiency in VHDL and/or Verilog and/or SystemVerilog
• Good knowledge of ASIC and FPGA environments
• Experience with systems integrating a RISC-V CPU or equivalent
• Scripting skills in Python for design and test flow automation
• Ability to work independently and in collaboration with multiple teams
• Fluency in French and English, both written and spoken
• Autonomous, rigorous, and able to work independently