Senior CMOS Analog/Mixed-Signal Engineer - NVM Memory

Ferroelectric Memory

Grenoble

Sur place

EUR 70 000 - 110 000

Plein temps

14 jours+
Générateur de candidature

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Résumé du poste

Ferroelectric Memory is seeking an experienced IC Design Engineer specializing in CMOS analog/mixed-signal design and emerging NVM devices to advance hafnium oxide ferroelectric memory tech. You will collaborate with global teams in Milan or Dresden to convert memory concepts into silicon.

The role requires a 5–10 year background in CMOS analog/mixed-signal design, hands-on Cadence and Verilog experience, and strong problem-solving skills in a cross-functional setting.

Qualifications

  • 5-10 years of experience in CMOS analog/mixed-signal design.
  • Experience with NVM device design for memory products.
  • Proficient with Cadence design environment and Verilog for modeling or verification.
  • Familiar with Cadence DFII, Virtuoso, Spice, and Verilog-A.

Responsabilités

  • Design and develop emerging NVM memory devices based on hafnium oxide technology.
  • Define specifications and support integration of analog and mixed-signal blocks into memory architecture.
  • Design analog circuits for NVM memories (sense amps, decoders, bandgaps, HV regulators, ADCs).
  • Run PVT simulations and circuit verification, including parasitic extraction.
  • Collaborate with layout engineers to optimize robustness, matching and area.
  • Contribute to post-silicon verification, debugging and optimization of memory IP and test chips.

Connaissances

CMOS IC design
Analog/Mixed-Signal
NVM device design
Cadence
Verilog
C programming

Formation

Electrical Engineering degree

Outils

Cadence tools
Virtuoso
Spice

Description du poste

Ferroelectric Memory is seeking an experienced IC Design Engineer specializing in CMOS analog/mixed-signal design and emerging NVM devices to advance hafnium oxide ferroelectric memory tech. You will collaborate with global teams in Milan or Dresden to convert memory concepts into silicon.

The role requires a 5–10 year background in CMOS analog/mixed-signal design, hands-on Cadence and Verilog experience, and strong problem-solving skills in a cross-functional setting.

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