MSB SSD NPM Technician – NPI & Shift Ops
micron
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Job summary
Micron Technology, Inc. is seeking an NPI Execution Support role focused on daily NPI lot execution, readiness tracking, and cross-functional coordination across SSD NPI and manufacturing teams.
The candidate will monitor NPI lot status, assist in expediting lots to meet dates, and support shift execution with tool readiness, process tracking, and documentation updates. A Nitec/Higher Nitec or Engineering Diploma is required, with 0–3 years in semiconductor operations.
Qualifications
- 0–3 years experience in semiconductor assembly, manufacturing, or operations support.
- Familiarity with cleanroom operations is an advantage.
- Basic knowledge of NPI flows is preferred.
- Nitec/Higher Nitec/Diploma in Engineering (Manufacturing, Mechanical, Electrical, Industrial, or related).
Responsibilities
- Support daily NPI lot execution across SSD.
- Monitor NPI lots status (WIP, holds, rework, conversion, disposition) and highlight risks.
- Assist in expediting NPI lots to meet dates.
- Track build readiness (material availability, tooling, DID, recipe, conversion readiness).
- Support daily shift execution by tracking tool readiness, downtime, conversion issues, process abnormalities, and holds.
- Help prepare and update daily execution trackers, WIP lists, and action logs.
- Escalate execution blockers promptly to responsible owners.
- Work closely with NPI / NPM engineers, Assembly Process & Equipment Engineers, CEM / IPPC / Manufacturing teams, and SSD NPM.
- Support interteam communication to ensure correct priorities for NPI lots.
Job description
Micron Technology, Inc. is seeking an NPI Execution Support role focused on daily NPI lot execution, readiness tracking, and cross-functional coordination across SSD NPI and manufacturing teams.
The candidate will monitor NPI lot status, assist in expediting lots to meet dates, and support shift execution with tool readiness, process tracking, and documentation updates. A Nitec/Higher Nitec or Engineering Diploma is required, with 0–3 years in semiconductor operations.
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