Innovative Standard Cell Library Characterization Engineer

Microchip Technology Inc.; Rousset-Serre-Ponçon; On-site; EUR 65,000 - 95,000; Full time

Job summary

Microchip Technology Inc. seeks a skilled Standard Cell Library Characterization Engineer to join the IP development team. You will characterize libraries across multiple nodes, delivering silicon-accurate timing, power, and noise models for successful SoC design closure.

You will generate Liberty models, develop feature-rich characterization flows, and validate results with SPICE simulations, while collaborating with circuit designers to resolve correlation issues and accelerate delivery.

Qualifications

• Master's degree in Electrical Engineering or related field.
• Strong understanding of CMOS circuit design and timing arcs.
• Experience with Liberty syntax and LVF modeling.
• Proficiency in Python, TCL, Perl or Shell scripting.
• Hands-on experience with standard cell characterization and SPICE tools.

Responsibilities

• Characterize standard cell libraries for timing, power, and noise across PVT corners.
• Generate and validate Liberty (.lib) models for synthesis and STA flows.
• Develop and maintain characterization tool flows using Cadence Liberate and Synopsys tools.
• Run SPICE simulations (HSPICE, FineSim, Spectre) for cell-level characterization.
• QA validation and cross-functional debugging of correlation issues.
• Support LVF characterization for advanced nodes and automate workflows.
• Collaborate with circuit designers to improve accuracy and deliver on time.

Skills

CMOS circuit design

Timing analysis

Liberty / LVF modeling

Python scripting

TCL / Shell scripting

Debugging / analytical skills

Education

Master's degree in Electrical Engineering

Tools

Cadence Liberate

Synopsys SiliconSmart

PrimeLib

HSPICE / FineSim / Spectre

Job description

Microchip Technology Inc. seeks a skilled Standard Cell Library Characterization Engineer to join the IP development team. You will characterize libraries across multiple nodes, delivering silicon-accurate timing, power, and noise models for successful SoC design closure.

You will generate Liberty models, develop feature-rich characterization flows, and validate results with SPICE simulations, while collaborating with circuit designers to resolve correlation issues and accelerate delivery.