FY27 Intern- AI-Driven Power Modeling for Evaluating Power Management Mechanisms in NoC Architectures - Guyancourt, 6 months

Qualcomm; Guyancourt; On-site; EUR 12,000 - 17,000; Full time

Benefits offered by this job

Paid internship

Job summary

Qualcomm France S.A.R.L. in Guyancourt is offering a 6-month paid internship in the Interns Group. You will research the impact of power management on NoC architectures and develop an AI/ML-based power modeling framework to estimate power during early design stages.

The project covers the design of control-plane NoC with power-management IPs, data-driven power characterization, and training ML models (ANN/MLP, RF, GNN) to enable fast, power-aware exploration.

Qualifications

• Final-year master's degree in Microelectronics, Computer Engineering or related field.
• Strong scripting in Python and bash; familiarity with Verilog/VHDL, UVM, and ML frameworks is a plus.
• Proficient in English; able to communicate in a technical environment.

Responsibilities

• Design & scenario setup for power-management NoC with IPs and traffic scenarios.
• Perform power characterization using synthesis and timing simulations.
• Construct a labeled dataset mapping traffic, activity, frequency and architecture to power.
• Train and compare ML models (ANN/MLP, RF, GNN) for power modeling.
• Support design-space exploration using trained models to guide architecture decisions.

Skills

Python

Bash

Verilog/VHDL

UVM

ML frameworks

English proficiency

Education

Final-year master’s degree in Microelectronics or Computer Engineering

Tools

NoC/IPS design

EDA flows

Power estimation tools

Job description

Company:

Qualcomm France S.A.R.L.

Job Area:

Interns Group, Interns Group > Interim Intern

General Summary:

ABSTRACT

This internship investigates the impact of power management mechanisms on Network-on-Chip (NoC) architectures and develops an AI/ML-based power modeling framework to estimate power consumption during early design stages. The objective is to enable fast and accurate evaluation of design choices while accounting for the effects of power-management components, thereby facilitating power-aware architectural optimization.

CONTEXT

QITC develops and deploys highly configurable custom-built NoC IPs, tools and methodologies so that worldwide SoC teams can assemble SoCs with the desired Power-Performance-Area (PPA) characteristics. Power-management components such as the Clock Domain Manager (CDM) and the Power Control Manager (PCM) directly shape the power profile of the interconnect, yet their impact can today only be quantified late in the flow, through synthesis, gate-level simulation and power analysis. Repeating this flow for every architectural option is prohibitively slow, which limits early power-aware exploration.

MISSION & METHOD

• 1. Design & scenario setup — Elaborate the control-plane NoC with its power-management IPs, and define representative traffic scenarios (idle, burst, mixed) across CDM and PCM operating modes, frequencies and technology corners.
• 2. Power characterization — Run synthesis and timing simulations to capture switching activity (VCD/SAIF), then extract static (leakage) and dynamic power with Synopsys power estimation tools (e.g. PowerArtist / PrimePower).
• 3. Dataset construction — Build a labelled dataset mapping traffic statistics, switching activity, frequency, technology and high-level architectural/system parameters to the measured static and dynamic power — achieving the first objective: quantifying the power cost of power-management mechanisms in a real NoC.
• 4. AI power modeling — Train and compare Artificial Neural Networks (ANN/MLP), Random Forest regressors and graph-based models (GNNs exploiting the NoC topology); assess accuracy against gate-level references (MSE, R, relative error), scalability and technology transferability.
• 5. Early design-space exploration — Use the trained models to explore design and power-management alternatives in seconds rather than hours, supporting power-aware decisions from architecture definition down to tape-out.

EXPECTED DELIVERABLES

• An automated characterization flow (simulation > activity extraction > power estimation) for NoC designs with CDM/PCM.
• A reusable power dataset and a benchmarked library of AI power models, with documented accuracy and speed-up assessment.
• A prototype exploration tool and guidelines for power-aware NoC architecture choices.

PROFILE & PRACTICAL INFORMATION

• Final-year master’s degree in Microelectronics, Computer Engineering or a related field; interest in digital design, low power and machine learning.
• Scripting in Python and bash; notions of Verilog/VHDL, UVM, EDA flows and ML frameworks are a plus. Proficient in English.
• Duration: 6 months, paid internship. Location: Qualcomm France, Parc Ariane, Guyancourt (QITC Deployment team).
• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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